Opening of the conference

The initial cost for producing a chip is very high. Therefore, getting the design right on the first run is essential. To identify potential errors in the design before production, considerable effort is invested in testing and verifying the design.

However, the current practice of chip design verification uses languages with roots in the 80s. The Doppio project aims to modernize verification tooling by leveraging insights from software testing. This paper introduces a software-based verification framework. We propose a framework using modern programming languages, such as Java and Scala, to verify digital circuits.

Bucket is an open-source Python project for collecting and viewing functional coverage, first presented at ORConf 2024. Since then Vypercore shut down, Noodle-Bytes took the project on, and Bucket has been picked up by two more silicon companies, one of which uses it to cover software rather than hardware. This talk covers the many changes from the last two years, including the improved viewer, comparing coverage between runs, and a new archive format, along with plans for the future.

One of the major complaints often leveled against cocotb is performance. coconext is an experimental cocotb fork which involves a major redesign to solve this problem by providing a first-class cocotb-like C++ API, while retaining the existing Python cocotb API, and providing communication between the two via a friction-less binding layer. This allows users to write tests, models, monitors and drivers, and all the other pieces of a testbench entirely in C++, Python, or whatever mix they deem appropriate. This talk will go over the rationale, features, a demonstration of performance gained by moving functional modeling to coconext, and the future of this project and related projects.

In this talk, we'll share the latest on the ongoing effort to expand Verilator's verification capabilities. We'll provide insight into the following developments:

• Four-state logic support is becoming usable on an experimental branch.
• The constrained randomization work continues, with significant improvements to the quality of generated stimuli.
• On the UVM side, what remains is bugfixing and scheduling improvements.
• SVA is close to feature complete, and the remaining work is bringing it into full IEEE compliance.
• Update on coverage and the tooling around it.

Safety- and radiation-critical systems need fault-tolerant CPUs, but the available options are predominantly proprietary solutions. This talk will present the ongoing work on Triple Modular Redundancy configuration of the VeeR-EL2 core, an open source RISC-V CPU hosted by CHIPS Alliance. This talk covers the current state of the implementation and introduces new open source tooling around Verilator built to enable fault injection testing and used for verifying the VeeR-EL2 TMR configuration.

This talk takes a look at the Surfer waveform viewer for digital simulation with a focus on what has been added since last OrConf. This includes simulator integration, annotations, a memory viewer, and several new ways to customize what you see.

Over its 15 years of existence, FuseSoC has become the most widely used IP management solution with thousands of publicly available packages (with many more inside different companies and institutions) and a public IP core registry. Together with Edalize, FuseSoC's EDA flow manager which supports more than 50 EDA tools, we have end-to-end solution for managing IP and building, simulating or analyze larger designs.

As always, there are still things to do, and this presentation looks at the road ahead for FuseSoC and Edalize and what features are planned for the coming years.

APyTypes is a cross-platform Python library for simulating finite word-length effects in complex digital systems, intended for design exploration and bit-accurate co-verification. It provides configurable fixed-point and floating-point data types, including scalar, multidimensional array, and complex-valued classes. With a NumPy-like interface, APyTypes makes algorithm design simple while staying true to hardware. This talk introduces APyTypes, how it can be used, and potential future directions.

Software has had CI for two decades. Hardware still finds most of its bugs at the bench, even while we use incredible physics sims for film and ML. Hauksbee closes this gap: it takes a real PCB design file (KiCad, Eagle, Altium, or gerber-only), parses the circuit, and simulates the hardware on each commit, so a fault that used to cost a fab spin and a fornight fails in minutes instead.

The tool exists because of a blind spot. Tarski, an analogue neuromorphic accelerator built at the University of GAlway, had a bespoke emulator (requiring significant time investment to built) integrating the intended circuit in closed form. Fast, but structurally incapable of seeing miswirings, or unnaccounted for behaviour, because it only ever simulated the design we wanted, not what was built. Hauksbee simulates exactly what you have laid out in a PCB file.

This talk covers what that means in practice: partitioning a board so linear islands get fast matrix-exponential solves and nonlinear islands get MNA and Newton; co-simulating firmware against the analog board in lockstep so a GPIO the code drives moves the simulated copper; and validating it against ground truth. This included re-deriving the Raspberry Pi 4’s shipped USB-C fault cold, from spec thresholds alone, matched to the real physics to within 0.01%.

I’ll also cover what happened when the tool was pointed at unreviewed, open-source boards: three previously unreported hardware defects, and one firmware-triggered ignition fault only a copper-to-silicon-to-firmware co-sim could have caught.

The effectiveness of a branch predictor varies significantly across software workloads, making it difficult to select and tune an appropriate predictor configuration without detailed insight into prediction accuracy and misprediction behavior. Existing approaches often require RTL instrumentation, dedicated performance counters, or processor-specific modifications.

We address this problem with a framework based on the Waveform Analysis Language (WAL), using the CVA6 open-source RISC-V processor as a case study. By analyzing branch-prediction behavior directly from simulation waveforms across benchmarks such as Dhrystone and CoreMark, the framework enables non-intrusive, workload-specific evaluation and supports informed configuration and microarchitectural exploration.

GVSoC is a configurable, event-driven simulator designed for simulating IoT processors and complex system-on-chips (SoCs). Combining the efficiency of C++ models and Python configuration scripts, it allows fast prototyping and design exploration bypassing the limitations of slow RTL simulation. This presentation gives a quick introduction to the platform, the recent updates enabling the simulation of full-platform many-core systems, and integrations with other simulators to extend its functionality.

Hardware verification can be tedious but exciting. So why not automate the tedious parts?

Python-driven verification reduces the tedium, but only so far. Tools like Slang allow us to build flows that keep verification in step with an ever-changing RTL.

The first brings the SystemVerilog bind concept into a Python-driven verification environment. Say you need to cover hundreds of FIFOs that can back-pressure the system: how many are there, and how do you keep up when that number changes? Slang allows us to find every instance and attach the coverage automatically, with new FIFOs covered the moment they are added.

The second tackles a scarier gap. Your coverage numbers look green, but is there a block nobody ever pointed a testbench at, one everyone assumed someone else had verified? Slang enables us to produce a definitive list of exactly those blocks.

Many questions about a hardware design are about connectivity: what drives this signal, what does it fan out to, is there a combinational loop, does this path cross a clock domain? Slang Netlist is an open-source C++ library that answers these by building a bit-level dependency graph directly over an elaborated SystemVerilog RTL design. Working at the source level rather than lowering to gates keeps close correspondence to the RTL and compilation fast; building on the slang front end brings rich SystemVerilog support and optimised parsing, elaboration, and data-flow analyses; and it is easy to integrate with Python bindings. This talk covers how it works — turning slang's analyses into a queryable graph — how to use it via the CLI and Python, and several use cases, including synthesis-style lint checks and clock-domain-crossing (CDC) analysis.

Slang-server is a SystemVerilog language server that debuted last year at ORConf. It has custom client extensions for Vscode and Neovim that extend the LSP with hardware features, enhancing the functionality when a design is specified. This talk will go over features added in the last year, planned features and tools, and news in the related Slang ecosystem

Block-level verification of parameterised RTL relies on hand-written parameter sets chosen from designer intent, not the assembled design. As the SoC grows, the two drift, and that gap goes undetected, because what the design actually builds is known only after elaboration.

I present a Bazel build-integrated flow tool that derives block stimulus from the elaborated design: one cache-gated slang elaboration of the SoC top is inverted into a per-module manifest of the parameter tuples each module is really instantiated with, and each is run at test time through the block's existing testcases, deduplicated against hand-written corners with coverage merged across runs. Deriving configurations inside the build graph rather than committing them means new instantiations are verified on the next regression, with no manual refresh and no staleness. I discuss the load-time/execution-time boundary that shapes such flows and results from a widely instantiated block whose hand-written sweep was missing real configurations.

I'm working on an exploratory RISC-V VPU that scales to very large numbers of lanes. I've been developing it using only open-source tools, and the focus of the talk will be on that experience. I'll choose a small section of the design (probably a distributed systolic array that I'm currently working on) and use that design space exploration as an example.

As open-source hardware becomes increasingly complex, interoperability and reuse have become major challenges. While software development benefits from high-level data type abstractions, standardized interfaces, package ecosystems, and implementation-independent specifications, hardware development remains largely centered around implementation-specific RTL, making component integration, portability, and collaboration more difficult. We need to reduce these interoperability hurdles to make collaboration between community driven open-hardware efforts more effective.
Tydi is an open hardware interface standard that addresses this gap by providing a vendor and technology-agnostic specification language for hardware interfaces and dataflow architectures. Tydi describes an interface at a high level by 1) a datatype and 2) a set of behavior parameters. By a principled reduction of this high-level description to the hardware interface implementation, Tydi enables component reuse across designs, easy composition, and verification across hardware description languages. Integration with open-source HDL tooling further improves the user experience of hardware design.
This talk introduces Tydi and its growing ecosystem of open-source tooling. We will discuss how Tydi enables automatic generation of interface code and documentation, improves composability of hardware IP, and serves as a stable specification layer for emerging AI-assisted hardware design and debugging workflows. The presentation will also highlight ongoing developments in generator tooling and ecosystem integration, demonstrating how Tydi contributes to a more interoperable, vendor-independent open hardware ecosystem. By providing a common specification layer for hardware component interfaces, Tydi aims to do for open hardware what interface definition languages and package ecosystems have done for software; enable reusable building blocks that accelerate innovation and strengthen the open hardware commons.

This talk introduces the EuroCDP Open IP Library, a curated collection of reusable open-source Intellectual Property (Open IP) blocks covering digital, analog, mixed-signal, RF, and photonic design domains. The library forms part of the European chip design platform (EuroCDP) and provides openly accessible IPs that can accelerate and simplify Integrated Circuit (IC) development. The presentation will introduce the IP Readiness Level (IPRL) framework, describing the definition of each level and the associated maturity milestones used to assess the quality and reuse readiness of Open IPs. It will also present the structure and organization of the Open IP Library, together with the standardized format adopted for each Open IP entry, including metadata, documentation, and evaluation criteria. Finally, the talk will provide an overview of the resources that Will support the assessment, discovery, and reuse of Open IPs within EuroCDP.

At Expected IT, a team of talented digital design and verification engineers works on chip development for AI and scale-up servers in the data center. We chose to use open-source EDA tools for chip development as much as possible and so far, we are pretty successful. One of our modules is a high-performance cache directory, orchestrating cache coherency in a multi-CPU system. While designing the directory, building blocks are developed that are not available already as Chisel components. These are sometimes generic enough to be useful for others. As such, we contribute the digital design IP of a component that performs resource allocation management. The circuitry manages a set of shared resources in a scalable, area-efficient way. The component is suited for high-frequency designs.

Dyno-SV is an open synthesis tool based on Dyno-IR (dynamic object IR), first presented at last year's ORConf. Much has happened since then, so time for an updated talk! Among the many things we worked on is memory inference, an integrated simulator for transformation verification, and various synthesis improvements. We'll go over these and more in the talk!

Spade is a Hardware Description Language inspired by modern software languages. I've presented the language itself several times at FOSSi conferences, so this time the focus will be on what you can build with it. I will present a few projects from obvious things like Risc-V cores, serious things like an ethernet and camera stack, and fun things like a pure RTL UI library.

This talk demonstrates the programmability of the Simodense RISC-V softcore running on an FPGA 1. The latest experimentation based on Simodense features runtime reconfigurability. Custom instructions can automatically be loaded during runtime on demand, using a recently proposed approach called "LUTstructions". LUTstructions are small FPGAs (essentially FPGA-on-FPGA when running on an FPGA) that are optimised for instruction implementation and fast reconfiguration 2. The prototype is entirely written in Verilog and is thus applicable to a variety of usage scenarios.

1 "Simodense: a RISC-V softcore for custom SIMD instructions" (GitHub repository) https://github.com/pphilippos/simodense

2 Philippos Papaphilippou "LUTstructions: Fast-Reconfigurable FPGA-Based Instructions" (in-press) IEEE/SBC SBAC-PAD 2026

For a long time, one of the crucial items missing in the open silicon ecosystem has been a formal equivalence‑checking tool capable of verifying modern‑scale architectures. Kepler‑formal provides exactly that, with an advanced multi‑threaded C++ core that can handle even large designs in a timely fashion. This tool adds another important building block in the journey toward industrial‑level development with open‑source EDA. It has already been adopted publicly by several key players in the open silicon community and also saw usage in the industry. In this talk, we will present the tool and its use model, as well as our roadmap in terms of format support and features.

https://github.com/keplertech/kepler-formal

While building netlist tools at keplertech.io, we kept missing a lightweight schematic viewer for browsing design connectivity and hierarchy. naja-schematic has been an internal project we'd now like to open to the community for use and collaboration. It's a small, fast viewer in C++ leveraging Dear ImGui for portability and WebAssembly capabilities. It currently loads naja data structures, but we are looking for ways to offer a general way to load any data structure.

Every EDA tool reimplements its own LEF/DEF/GDSII/Tcl readers. rawast replaces them with one universal engine where the grammar is data — a runtime .rawast file, not compiled code. One engine parses any text or binary format into a queryable value tree, and because it’s bidirectional, the same grammar re-emits the text too. It’s self-hosting, GDSII is the worked binary example, and a planned container lets downstream tools parse once and never re-parse. The PoC parses a 3,132-file production corpus across four formats. C++17 + Python, MIT.

Where do the liberty files come from? How to create own liberty files with open source tools? This talk introduces OpenChar, a new open-source standard cell library characterizer. OpenChar uses NGSpice to simulate standard cells and generate liberty files and Verilog models for them. The talk will focus on user visible features and compare OpenChar with other existing open-source solutions. We briefly look at the internal workings of OpenChar, and since SW is never finished, we will also talk about missing features and future plans.

Logic synthesis is a key step in the chip design flow. By abstracting away many physical implementation details, it has also provided a fertile platform for academic research. At UC Berkeley, this line of work began with ESPRESSO and SIS and later achieved broad impact with ABC, which has become a foundation for much of modern logic synthesis research and serves as the core optimization engine in Yosys. More recently, mockturtle, developed at EPFL, has revisited and refined many synthesis algorithms in a clean, modern C++ framework, emerging as an important new platform for research.

This presentation will give an overview of these open-source logic synthesis efforts. We will first introduce the core intermediate representations and state-of-the-art optimization techniques. We will then discuss directions for the next generation of synthesis, including hierarchical and word-level optimization upstream and physically aware optimization downstream, as well as practical benchmarks from the PULP platform developed at UniBo and ETHZ to help drive improvements in synthesis tools.

RISC-V ISA extensions such as Vector introduce large configuration spaces and subtle corner cases that make RTL verification and debugging increasingly challenging.

This talk presents RVVTS, an open-source framework for automated testing of complex RISC-V ISA extensions at RTL. RVVTS combines grammar-based test generation, differential execution against architectural reference models, failure isolation and test case minimization, and automated failure analysis to categorize and characterize detected mismatches.

Using the RISC-V Vector and Floating-Point implementations in the open-source PULP Ara processor as case studies, we show how RVVTS turns large numbers of test failures into compact, reproducible, and actionable failure reports, significantly reducing the manual effort required for RTL verification and debugging.

ShapeIC is an open-source project for fast design-space exploration of analog integrated circuits. Instead of running a full circuit simulation for every candidate, ShapeIC characterizes devices and circuit primitives using lookup tables and reuses this data during hierarchical exploration.

This talk will introduce the basic ShapeIC flow and some of the challenges that appear when LUT-based exploration is applied to real transistor sizing. It will also show how the same approach can be extended to include layout-dependent parasitics without running full layout extraction for every candidate.

Finally, I will present the current state of the project, its limitations, and the direction we want to take ShapeIC next.

The key for end-to-end open source HW are OpenPDKs released by the manufacturers. At the moment, there are a handful of OpenPDKs, and we need more. In this talk I will summarize the case for Open PDKs and why they are more important than you think, the issues that are raised by manufacturers and finally what we have been doing recently to advocate for more Open PDKs.

The IHP SG13G2 Open PDK has evolved into an increasingly complete platform for digital, analogue, mixed-signal and RF integrated-circuit design. This presentation focuses on recent technical progress and on the practical path from an open design environment to fabricated silicon. Updates across the SG13G2 ecosystem include digital libraries, device models for ngspice and Xyce, schematic capture with xschem and Qucs-S, KLayout-based parameterized cells and verification, Magic support and digital implementation using OpenROAD-flow-scripts and LibreLane. The talk will assess the preview release’s current maturity, limitations and development priorities. The second part presents IHP’s open-source Multi-Project Wafer activities and lessons from recent SG13G2 tape-outs. It introduces IHP’s low-cost Open-Silicon MPW model, through which openly licensed, reproducible designs can be fabricated and published in a dedicated GitHub repository. These activities also underpin IHP-led Work Package 3 of ODE4EC-AMS, which will validate SG13G2 and SG13G2Cu PDK integration and open-source IP through MPW tape-outs and silicon measurements. Finally, the talk explains the practical route for participating in upcoming open runs – from registration and design publication to verification, tape-in and delivery – and outlines planned PDK improvements and future fabrication opportunities.

Open-source silicon has advanced rapidly for digital design, yet the analogue, mixed-signal (AMS) and RF domain remains the ecosystem's hardest gap-with fragmented flows, missing or immature tools, and open PDKs that seldom support a complete AMS path. This presentation introduces ODE4EC-AMS (Open Design Environment for European Chips - Analogue and Mixed Signal, Project No. 101252962), a three-year initiative funded by the Chips Joint Undertaking and carried out by a consortium of research institutes, universities and industry partners, created to close that gap by strengthening and connecting the open-source tools designers already rely on rather than replacing them. Starting in June 2026, the project aims to make mature technology nodes accessible for AMS product development and to lower the barrier to entry for SMEs and start-ups, and this talk maps its planned scope across the flow: improved open electromagnetic, RF and mixed-signal simulation and parasitic extraction (building on tools such as ElmerFEM, ngspice, Magic and KLayout-PEX), an automated framework for generating AMS and RF IP and layout, integration of these advances into open PDKs validated through Multi-Project Wafer (MPW) runs, and openly licensed training material to support wider adoption. As an early-stage introduction, the talk emphasises transparency and community-sharing the roadmap openly, explaining how results will be released under open licenses and sustained beyond the project's lifetime, and, above all, inviting the open-source hardware community to follow, test, use and contribute to the outcomes from day one.

Since introducing the IHP Open PDK and its accompanying open-source design flows, the ecosystem has continued to evolve well beyond its initial infrastructure. This presentation highlights recent milestones and provides an outlook on the next steps toward a broader and more accessible open hardware ecosystem. The talk begins with an update on the DI-OCDCpro project (Funding Code: 16ME0940), including the first collaborative chip designs submitted for fabrication through IHP's Multi-Project Wafer (MPW) program and an overview of the upcoming activities planned together with the project partners. Another focus is SG13CMOS5L, a CMOS-only technology variant that recently reached its first tape-out. Originally initiated within the DI-OCDCpro project, SG13CMOS5L is designed as a fast and cost-effective platform for education, student projects, prototyping and future open design challenges, while remaining fully compatible with the existing open-source ecosystem. Finally, the presentation concludes with an outlook on future community activities. Building on the experience gained so far, the talk will present the vision for additional open design challenges currently under preparation, aiming to further lower the barrier to ASIC design, strengthen collaboration within the open-source hardware community, and create new opportunities for education and hands-on chip design.

This talk will outline the activities and objectives of the CHIPS Alliance and newly formed OpenROAD initiative organizations.

The OpenROAD initiative is a non-profit organization focusing on making chip design open and accessible to all.

CHIPS Alliance hosts open source tools and IP blocks for ASIC development, and has a vision of aligning open source efforts towards building a tool suite for faster and more collaborative design and testing of silicon. The talk will discuss restructured SV Tools and VeeR projects as well as new developments in tools and cores hosted within CHIPS Alliance.

Open-source EDA tools lower the barrier of entry to IC design by lowering tool costs, allow inspectability and modifiability, and reduce supply chain dependencies. This talk presents a summary of the state of open-source EDA tools for integrated circuit design. It describes the findings of analysis and the resulting report which have been carried out in the context of EuroCDP. The work covers the domains of digital, photonics, analog & mixed-signal and radio frequency design. The talk presents conclusions on the maturity of toolflows, and the results of a gap analysis which identified tool functionalities and features that are either missing or would benefit from further improvements.

Software reuse works because a registry tells you what you are getting and you can run the tests. Silicon reuse has meant tarballs and PDFs.

Vyges VyCatalog is an open, machine-readable registry for silicon IP. Each block carries validated metadata describing its real RTL interface, filesets, and bus and PDK targets, and a CLI resolves and stages blocks the way a package manager would.

Vyges Loom is the other half: an open sign-off suite — geometric DRC, LVS, RC extraction, and static timing with signal integrity — so you can check what you pulled instead of trusting a datasheet. It is a second opinion alongside magic, netgen, KLayout and OpenSTA, not a replacement. Critical path delay correlates within about 1.6% of OpenSTA on synthesized sky130 designs.

The talk shows both, and the limits of each. https://vyges.com

Matt Venn, founder of Tiny Tapeout will present some highlights from recent shuttles, give an update on the current status of the 3 open source PDKs and share plans and ideas for the next few years.

Packaged silicon parts have finally arrived on-site in time for summer 2026, including the second Chipalooza test chip on Sky130 and new 3.3V support for GF180MCU on the first Wafer.Space shuttle run. All circuits are functional! Characterization results will be presented for the several dozen analog blocks on the Chipalooza test chips as well as for the 3.3V SRAM and I/O library components. I will report on continuing efforts to provide open source analog libraries for all of the open PDKs.

wafer.space provides budget silicon manufacturing for the GF180MCU process.

In this talk, we will take a look back at the wafer.space shuttle runs and the challenges that came with them. Furthermore, I will highlight a number of impressive open-source designs, as well as some very useful community-created IP. Finally, I will provide an outlook on ongoing and future developments.

Machine learning accelerators are frequently designed, simulated, and left as RTL — verified against a testbench, never carried through to physical implementation. This talk follows one such design: a K-Nearest-Neighbors classifier (K=7, squared Euclidean distance, 64-entry reference set, 16-bit fixed-point inputs) built as a Verilog controller-FSM and datapath.

I integrate it as a memory-mapped coprocessor on an open RISC-V core and push the design through the open-source RTL-to-GDSII flow — Yosys, OpenROAD, and the SkyWater SKY130 PDK. The talk presents the implementation flow end to end, reports synthesis and physical implementation results as achieved by the time of the conference, and highlights specific engineering trade-offs encountered moving from RTL simulation toward physical implementation; including where a brute-force, single-cycle 64-way distance computation becomes the critical path once timing closure is on the table. This is a concrete account of what the gap between "verified in simulation" and "ready for physical implementation" actually contains.

In this presentation the current state of project Arrakeen will be discussed. Focus will be on the advancements in the SRAM generator development done in the IHP FlowSpace project.

Memory arrays are typically the highest-defect-density block on a chip, yet the tools used to test and repair them at manufacturing time remain locked inside commercial EDA suites, with no real open-source equivalent.

AutoMBIST is an open-source generator that takes a memory macro from RTL through a genuine 2D row-and-column redundancy solver (BIRA, cross-validated against a brute-force oracle) and produces a synthesizable on-chip self-repair controller (BISR) that operates without any external tester. It has been demonstrated on real OpenRAM-compiled SKY130 SRAM macros, each wrapped in a full MBIST and self-repair block, hardened through LibreLane 3.0.5 to zero detailed-routing violations and clean LVS/power-aware signoff.

The talk covers the MBIST collar insertion & BIRA algorithm, a walkthrough of the autonomous on-chip self-repair flow, and the physical closure results.

This talk gives a brief update on improvements and new features in the FABulous eFPGA framework as well as a survey on newly designed chips that include a FABulous eFPGA (using SKY130, IHP CMOS5l, XFAB 180 and TSMC 28nm PDKs) as well as an outlook on our DI-OWAS chip that will feature a NEORV32 SoC, peripherals like a camera interface, and an eFPGA with attached AI accelerator to be fabricated in a 28 mm2 IHP 130 CMOS5L tapeout.

Over the last seven years I've been teaching digital hardware design and FPGA development at the University of Wrocław. Along the way, the limitations of existing educational tools led to the development of DigitalJS: a visual hardware simulator which connects HDL code to the circuits described by it. Later, the Transactron library was developed in order to provide reliable hardware abstractions upon which the Coreblocks out-of-order CPU could be built.

This talk tells that story. I'll show how each project came about and how they made a difference in the teaching process. I'll also share what surprised me about teaching hardware, which concepts students consistently struggle with, and how open-source tools can lower the barrier to learning advanced computer architecture. As my background is in computer software (and programming languages in particular), I'll put some emphasis on how software and hardware worlds differ and what can they learn from each other.

[Vulkos](https://vulkos.co.uk] is a free, browser-based platform for young students and entry-level engineers to learn and practice chip design, verification and analysis using agentic AI. In this presentation, we'll demo some of the key features, student creations and future developments - and within 5 minutes we plan to do a live demo going from the sign up page to a verified, tapeout-ready GDS.

Design rule checking is one of the last steps between a layout and a tape-out — and, in a fully open flow, often one of the slowest. Running IHP's SG13G2 rule deck through KLayout takes long enough to break the edit-check-fix loop, and because the deck is written for one engine and shipped inside the PDK, it is neither easy to reuse nor easy to run in isolation.

gdscheck grew out of a simple set of requirements: a DRC engine that saturates every core of a workstation instead of one; that carries its rules with it, so no PDK installation is needed to check a GDSII file; that lets a user run a single layer deck or a curated suite without writing a line of script; and that is regression-tested against per-rule test patterns, so a rule change cannot silently break a PDK.

This talk introduces gdscheck, an open-source DRC engine written in Rust. Rules are declarative YAML decks referencing layers by name; the hierarchy is flattened up front; every check fans out with rayon, with bounding-box pre-filters and a sweep-line search keeping spacing checks near-linear. Violations are written to a KLayout-compatible .lyrdb, so existing debug workflows are unchanged.

I will close with benchmark results against the reference flow on real SG13G2 designs, and outline what is still missing before the tool can be trusted for sign-off.

Mapping algorithms to area-efficient, time-multiplexed hardware architectures that meets the specifications is a non-trivial task, particularly with respect to scheduling, resource assignment, and generation of control logic. Manual pen-and-paper design is typically both difficult and error prone. B-ASIC is an open-source Python framework for the design and implementation of static algorithms. From capturing the algorithm as a signal-flow graph, through simulation and mapping, to automatic generation of synthesizable RTL and testbenches. In contrast to typical high-level synthesis flows, where the designer has limited influence over the resulting architecture, B-ASIC provides designers with granular control over operator and memory selection, scheduling, resource assignment, pipelining of control signals, and I/O.

Open-source digital ASIC design flows have matured considerably, and the ecosystem for analog and mixed-signal design is also expanding. Open PDKs, circuit simulators, design tools, libraries, and new community projects are making open-source AMS design increasingly accessible.

This talk will give a brief overview of the current state of open-source AMS verification and present SpiceBind, a project that connects ngspice to a VPI-capable HDL simulator. SpiceBind allows an RTL block to be replaced by its SPICE implementation while keeping the existing HDL or cocotb testbench and the familiar waveform and debug flow. This provides a simple way to include transistor-level circuits in an RTL verification environment.

A parameterizable multi-speed Ethernet Media Access Control (MAC) design generator covering data rates from 10 Mb/s up to 10 Gb/s has been developed in Chisel. Besides implementing various PHY-side interfaces, such as MII, GMII, RGMII, SGMII, XGMII, as well as MDIO for PHY management, and system-side interfaces, such as AXI4-Stream and TileLink, it also includes Direct Memory Access (DMA) and hardware support for ARP, IPv4, and UDP protocols, thereby forming a versatile hardware networking stack.

Within the scope of the RIVET project, the implemented components are further integrated into Chipyard, the open-source framework for agile development of RISC-V Systems-on-Chip (SoCs). As a result, designers and engineers can now equip custom ASIC- and FPGA-based compute systems with flexible, reusable, and "plug-and-play" networking functionality rather than developing and integrating Ethernet infrastructure from scratch.

"Ethernet MAC Hardware Design Generator" (GitHub repository) https://github.com/ucb-bar/ethernet-mac

"Cointegration of RISC-V Systems with Ethernet" (RIVET project) https://nlnet.nl/project/RIVET

The Borg (Bring yer Own GRaphics) project—supported by NLnet—is establishing a fully transparent, end-to-end silicon implementation flow for open-source GPU hardware using a 100% libre EDA toolchain. Recognizing that full GPU development is highly complex, the initiative capitalizes on recent advances in low-cost chip manufacturing to make individual tape-outs feasible for small teams.

Hardware description languages traditionally describe a circuit and leave optimization largely to the synthesis flow. Spire explores a different approach: a Python-embedded HDL in which optimization is part of the language and compilation flow. Spire lets designers express optimization intent directly in the source and applies transformations such as arithmetic architecture selection and fusion, FSM minimization, and logic optimization using ABC.

This talk presents the concepts behind Spire and shows, through examples and quantitative results, how it can produce smaller and faster circuits than conventional Verilog/Yosys flows. We also show how Spire is used by RTLScout, where LLM agents can explore optimization choices beyond rewriting RTL code.

Finally, we discuss lessons learned and which ideas and reusable optimization components, such as Spire's arithmetic library, could benefit Yosys and the broader open-source EDA ecosystem.

https://github.com/huawei-csl/spire-hdl

Large Language Models (LLMs) are rapidly transforming hardware design, yet evaluating their true ability to generate correct Register-Transfer Level (RTL) code remains a moving target. Existing static benchmarks suffer heavily from data contamination, as newer models are continuously trained on open-source repositories containing the test questions themselves.

To break this cycle, we introduce NotSoTiny, an automated, living evaluation benchmark that turns the vibrant Tiny Tapeout open-source ecosystem into a continuous source of fresh evaluation data. Following its appearance at DAC 2026, this talk brings NotSoTiny home to the FOSSi community to explore how crowdsourced physical silicon designs and tools can drive the future of AI for chip desing.

NotSoTiny automatically ingests new designs from consecutive Tiny Tapeout shuttles. By leveraging an open-source evaluation pipeline built on formal verification and automated linting, it cleans duplicates and generates complex, structurally rich module-completion tasks. Because the dataset updates dynamically, it provides a contamination-resistant sandbox that reflects actual, human-designed hardware challenges.

In this presentation, we will detail the architecture of the NotSoTiny pipeline, share insights from evaluating state-of-the-art LLMs, and discuss how the open-source community can contribute to accelerate trustworthy AI-driven chip design.

AI agents can nowadays write and check RTL, and more recently even push designs toward tapeout. This talk presents three open-source agentic tools to assist with these goals from different angles. RTLForge is a LLM-orchestrated verification-grounded pipeline that automates RTL design process and doubles as a harness for LLM finetuning and training. Chipchamp is an agentic coding-harness for chip design : it plans, edits RTL, and drives open-source flows from the terminal. Alwavelets is a Python-based lightweight VCD/FST waveform viewer that runs entirely in the terminal, so you can debug over SSH or expose using MCP where the agents can take control. I'll show each briefly, say plainly what they do and don't do yet, and where contributions would help.

AI agents can already execute EDA commands, but reliable chip-design automation requires more than shell access. Every tool has different invocation rules, environment assumptions, artifacts, logs, and definitions of success. This makes agent workflows difficult to reproduce, audit, and move between tools.

OpenADA is an open-source semantic interface between AI agents and open EDA tools. An agent expresses an engineering intent—such as netlisting a schematic, running a circuit simulation, checking DRC, comparing LVS, or structurally checking RTL—and OpenADA translates it into a deterministic native-tool operation. It returns structured evidence, including separate execution and engineering status, diagnostics, artifact hashes, provenance, and the assumptions affecting interpretation.

This talk presents OpenADA’s architecture and its current integrations with Xschem, ngspice, Xyce, KLayout, Netgen, and Yosys. A demonstration will show the same circuit-simulation intent executed through ngspice and Xyce while retaining each simulator’s native artifacts. The talk will explain how an open semantic contract can let EDA maintainers integrate once, allow researchers to swap backends, and keep agent-generated engineering results reviewable instead of reducing them to unbounded log summaries.

CIRCT is a powerful and flexible framework for hardware development. Within the OSVISE project we introduce an exchange at IR level between CIRCT and Yosys and Verilator. This enables a design exchange without SystemVerilog involvement and new capabilities.

Functional coverage is trusted as the record of what's been verified, but the constructs used to write it — covergroup, coverpoint, bins, cross — have a huge impact on verification that never show up as compile errors. A covergroup can compile cleanly and still be suboptimal:

1. Consider: illegal_bins masking a real design bug instead of letting SVA or a scoreboard catch it;
2. At a subsystem with multiple instances of the same IP, merge_instances hiding per-instance holes behind an aggregate that looks complete
3. Huge performance degradation due to implicit edge-triggered sampling quietly running every clock cycle instead of at the transaction boundary.

These are methodology and performance bugs, not syntax errors, so nothing in the normal compile-and-simulate flow flags them.

FCOVLint is a static lint tool built for exactly this gap. It checks 20+ rules across four areas: coverage-methodology soundness, sampling and cross-coverage performance, style and maintainability, and constructs that are legal SystemVerilog but unsupported or ill-defined under Verilator specifically.

This talk walks through the rule set, how each pattern is detected in SystemVerilog source, and worked examples of what gets caught — a masked bug, a false sense of completeness, a performance cliff, or a Verilator compatibility gap.

Repo: https://github.com/AsFigo/FCOVLint

Our RISC-V chip ran out of area, so memory had to go off-chip. HyperRAM was overkill, and every open-source SPI controller I could find had already committed to one specific chip. I have commitment issues, so I built a QSPI controller that doesn't care: fully software-defined command frames, CSR and memory-mapped XIP modes, no clock domain crossing. Verified in simulation, validated on real hardware with an open FPGA flow and soon to be silicon proven.

Generated RTL is normally evaluated by whether it passes its checks, which is unreliable when the checks are generated too. We report a failure attribution study on a flow where one open-weight model generates Verilog from an engineer-written specification and a second model generates a cocotb testbench from the same specification, with no access to the generated RTL. The isolation is structural: the record the testbench generator receives has no representation for RTL and is constructed before any RTL exists.

Regenerating testbenches for thirty blocks five times each, with sampling disabled, gave identical output in only seven cases, which invalidates single-run measurement. Across five runs of 118 acceptance checks, 83 passed consistently, 26 failed consistently, and 9 were unstable. Of the consistent failures attributed so far, eight are defects in the generated testbench and four in the execution infrastructure. None are in the generated RTL.

Machine learning can enable early-stage prediction of important design characteristics, such as routing congestion, allowing potential design issues to be identified before computationally expensive physical design stages. In this talk, we introduce EDABench, a framework that integrates machine learning workflows into LibreLane, an open-source EDA toolchain, with automated dataset curation, feature extraction, ML model training, and evaluation. We further study the generalisability of ML models across EDA tools, PDKs, and designs, including whether models trained using commercial EDA tools such as Cadence can generalise to open-source EDA toolchains.

Radiation tolerance of digital circuits requires that single event upsets (SEUs) be mitigated by automatic detection and correction. The most common method is triple voting: Replacing each flip flop with three plus a majority voting cell. This effectively guards against the vanishingly improbable case of suffering thousands of SEUs simultaneously across a chip. I present a method in which synthesis can automatically detect flip flop arrays and replace them with an efficient ECC (error correction code) scheme automatically, reducing a ~2N area hit for N flip flops to ~2log(N).

In this lightning talk I will give an overview of a recently completed project to bring up the open source ExecuTorch AI framework on a low power microcontroller, the CORE-V CV32E40Pv2. I will show briefly how we used the unique features of this open source hardware design to accelerate AI inference., This project, carried out in partnership with Mosaic SoC, yielded an implementation capable of running real world edge AI applications.