A new approach in digital electronics design for FPGAs has recently arisen, featuring advanced packaging, versioning and dependency management capabilities for gateware HDL design. Strongly based on Guix dependency manager, this approach departs from traditional methods and opens the door to a fully declarative paradigm on dependency handling, including transactions and determinism, which guarantees traceability during the full design cycle. It is thus possible to treat IP Blocks as any other project requirement -including software-, in addition to producing fully reproducible environments and container images, facilitating the path towards modern continuous integration practices. User custom dedicated repositories allow the development of all that's necessary to build (hdlmake), simulate (ghdl), and synthesize (yosys) designs remotely, using unit testing frameworks (vunit) and modern verification libraries (osvvm), in addition to performing cosimulation (cocotb) in remote forges.

The design of advanced chips‚ especially in photonics, quantum, MEMS, and RF, faces critical challenges due to rigid, outdated EDA tools. Many teams resort to custom Python, C, or MATLAB solutions, which offer flexibility but lack scalability. To bridge this gap, we created GDSFactory, an open-source, python-based Analog Electronic Design Automation software that has been downloaded over 2 million times and adopted by companies, universities, and research organizations worldwide.

Tiliqua is an open hardware development platform, DSP library and collection of examples (built in Amaranth HDL) that aims to make FPGA-based audio and video synthesis more accessible. This talk builds on last year's edition, this time covering some war stories from the past 12 months of getting Tiliqua hardware ready to ship, and all the new features added to the DSP/RTL library since then. We'll cover some fun topics such:

• Implementing low-latency USB host purely in gateware
• Dynamic frequency scaling for display switching
• New DSP cores and example projects
• How we are adding first-class fixed-point types to the Amaranth language
• Lessons learned from shipping hardware (and some tricks for passing CE/EMC)

As we walk through each theme, this talk will include some live demos on a small Eurorack system demonstrating each.

A FABulous FPGA utilizing the Panamax padframe designed using open source EDA tools and the open source sky130 PDK.

Panamax FPGA features 64 I/Os, 1280 LCs (LUT4+FF), 8 MAC (8-bit * 8-bit + 20-bit), 16 register files (1w2r, 32x4) and 8 BRAM (dual-ported 1r1rw, 256x32). In addition, the FPGA fabric integrates some analog IP: 2 x 12-bit split-CDAC SAR ADC and 2 x 8-bit R-DAC.

Panamax FPGA was submitted for tapeout in May 2025.

At the Barcelona Supercomputing Center (BSC) we are actively pushing research on LLMs for chip design. Our early contributions include an integrated evaluation framework (TuRTLe) to assess RTL code quality under syntax, functionality, synthesizability and PPA performance. Commited to open science, this is done in integration with open tools (Icarus, Yosis, OpenROAD), and publicly released for others to use and extend. This talk will include insights on the latest model performance, evaluation challenges and future research lines of work, towards improving the use of LLMs for EDA.

HAgent is an open-source Hardware Agent infrastructure that integrates LLMs with chip design tools through a compiler-inspired pipeline architecture. The framework enables AI-assisted hardware development across with hermetic passes that communicate via YAML interfaces for enhanced debuggability and reproducibility.

Based on experience of guiding engineering at a silicon startup using FOSS tools and a strategy of open sourcing where possible, this presentation will explore where that limit is today, lessons learnt from this strategy, and some tips for others considering such an approach.

Constrainedrandom is a Python package for - you guessed it - creating and solving constrained randomization problems. It's faster than PyVSC. It achieves this by walking the through state space randomly, rather than using exhaustive solutions for constraints. That makes it much faster for the majority case, though it's possible for it not to converge for harder problems.

Overview of our open-source Transactron library for Amaranth HDL language, how it makes designing complex hardware easier, modular, solid and fun, introduction to the concept and demos.

Designed to overcome the limitations of OpenLane but maintain its signature ease-of-configuration and ease-of-installation, LibreLane is the modular and extensible community-driven successor to the world's most popular open source EDA flow, reimagining it as not just a flow, but as a customizable ASIC data flow infrastructure. In this talk, we will outline what motivated us to make LibreLane, what it's currently capable of, and our future development plans, as well as a showcase of both simple and advanced use-cases it enables.

In computer architecture courses, we usually teach RISC processors using a five-stage pipeline, neglecting alternative organizations. This design choice, rooted in 1980s technology, may not be optimal today, and it is certainly not the easiest pipeline for education. This talk examines more straightforward pipeline organizations for RISC processors suitable for educational purposes and for implementing embedded processors in FPGAs and ASICs. We analyze resource costs and maximum clock frequency of various designs implemented in an FPGA, using clock frequency as a performance proxy. Additionally, we validate these results with ASIC designs synthesized using the open-source SkyWater130 process.

Contradictory to common wisdom, a longer pipeline (up to 5 stages) does not necessarily always increase the maximum clock frequency. In two FPGA and one ASIC implementation, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor.

Open-source digital verification has advanced rapidly, but mixed-signal designs still lack a seamless path into modern RTL testbenches. This talk surveys today's community-driven options, pinpointing their remaining pain points.

I then introduce SpiceBind, a lightweight VPI bridge that embeds an ngspice solver inside any VPI-capable simulator. RTL and SPICE devices step on the same timestep, while your existing testbench, coverage, and waveform tools remain unchanged.

A top-level case study demonstrates how SpiceBind drops into a typical RTL simulation, and runs unmodified in a CI workflow.

Attendees will leave with an entirely open-source, reproducible recipe for bringing mixed-signal verification into their designed.

Junit outputs from cocotb are a useful building block for maintaining Continuous Integration (CI) for silicon projects. This can be extended through the use of OpenMetrics and Grafana to provide dashboards to present useful metrics and insights such as test coverage over time, simulator usage or bug tracking.

yosys-slang is a free and open extension for Yosys adding support for SystemVerilog design input. It has been used in two tapeouts and is seeing growing adoption in the community. The talk will cover the tool's status, future plans, and opportunities for other tools to build on top of its codebase.

RV32I softcore and implementation from schematic to structural verilog (logilib) with verilator.

Sesenta: Open source FPGA based tileable acoustic camera sesenta is a tool for creation of acoustic cameras. has a modular design. It consists of 2 parts: the microphone array and FPGA based control boards. Each array is a board with a lattice of 60 microphones designed to work in conjunction with other arrays (tile of arrays). A Sesenta can work independently, but the ability to use it as a tile allows for an expanded range.

najaeda is a Python library that encapsulates naja, an advanced C++ open source framework for post synthesis netlist browsing and optimization. One of the prominent uses for najaeda by the community has been ECOs due to its ease of use, friendly API and installation. Licensed tools for ECOs can be costly and sometimes not dynamic enough. This results in a large number of engineers resorting to manual changes that can be time consuming and inconvenient. najaeda presents a reliable and straight forward open source alternative. In this talk we will do an overview of the library’s capabilities and our plan to integrate embedded verification infrastructure in order to meet industrial standards and provide the community with a fully open source alternative.

DRAMSys is the go-to tool for developers and engineers who need full transparency in product development with integrated DRAM subsystems. This advanced open-source simulation framework, built on the SystemC TLM-2.0 standard, delivers unmatched flexibility and performance. DRAMSys follows a Freemium model, combining open-source accessibility with commercial options. The latest memory standards—such as DDR5, LPDDR5, and HBM3—are available through commercial models distributed by Fraunhofer IESE, with the revenue supporting ongoing maintenance and the development of future memory technologies. Universities can benefit from free academic licenses. DRAMSys is widely used in Industry, e.g. by Rambus and Ateris. With DRAMSys, you can tackle the complexities of modern memory systems effortlessly. Whether analyzing bandwidth, latency, or power consumption, DRAMSys equips you with the tools to optimize your design. This talk will provide insights and real-world use cases of DRAMSys in action. (DRAMSys is a project in the German Design Initiative.)

Achieving robust timing closure is paramount in modern ASIC design. This talk delves into the critical role of physical synthesis and timing optimization within the OpenROAD flow, with a particular focus on its powerful Resizer module. We will begin by revisiting fundamental concepts essential for successful timing closure, including best practices for design constraint generation and the intricacies of handling multiple clock domains (MCDs) to avoid common pitfalls. Understanding these foundational elements is key to leveraging any optimization tool effectively.

Beyond the fundamentals, this presentation will highlight the significant recent advancements and capabilities integrated into OpenROAD's Resizer. We will explore how these updates enhance its ability to perform sophisticated gate sizing, buffer insertion, and netlist restructuring, leading to improved power, performance, and area (PPA) metrics. Attendees will gain practical insights into effectively constraining their designs and harnessing the latest features of the OpenROAD Resizer to achieve superior timing closure results for their open-source hardware projects.

As a young startup company, developing IP for AI and scale-up servers in the datacenter, we chose to use open-source EDA tools for chip development. One of our designs implements a high-performance cache directory, for orchestrating cache coherency in a multi-CPU system.

We show our front-end design process, and share our RTL design and verification experiences so far. As minor contribution, we propose some enhancements to Chisel that helped us improve our code quality.

Space electronics operate in an environment that demands the highest levels of reliability, radiation tolerance, and performance - under some of the harshest constraints on Size, Weight & Power (SWaP). Yet system designers are consistently faced with a painful choice: use off-the-shelf terrestrial chips that aren’t built for the mission, or rely on space-rated parts that are expensive, obsolete, and lacking performance.

At SPHERICAL, we’re solving this problem by collapsing the gap between chips and systems. We build high-reliability, high-performance space systems by designing our own mission-specific chips - enabled by open-source tools and a modern, software-first methodology. This approach lets us deliver systems that are not only more capable but radically more flexible, auditable, and scalable.

This talk will walk through our design philosophy, the tool flows we’ve developed and adapted, and how we’re leveraging the open-source silicon ecosystem to deliver 10x improvements in performance, reliability, and configurability. We’ll close by reflecting on the opportunities and missing pieces for the open-source community to power the next generation of critical systems.

B-ASIC is a work-in-progress open source framework for the design and implementation of static algorithms. Expressing an algorithm using a block diagram/signal flow graph, the algorithm can be simulated, including finite wordlengths. From that, the algorithm is mapped to hardware, by first scheduling the algorithm, extracting and mapping resources, resulting in an architecture. This can be done either manually, automatic or by a suitable combination, using the exact operations/processing elements that the designer finds suitable. A bit like high-level synthesis, but with more control of the steps. Finally, code describing major parts of the architecture can be generated.

APyTypes is a open source Python library, similar to NumPy, that provides fully parametrizable bit-exact scalar and array data types with either fixed-point or floating-point representation. This allows performing high-level simulations of finite word-length effect before implementing an algorithm. Implemented in C++, the library has significantly higher performance and/or are more complete than the alternatives. In this talk, APyTypes is introduced and it is shown how algorithms can be simulated and the results used for checking the implementation.

This talk briefly introduce the Surfer waveform viewer with a focus on recently added features and an outline of things that may be next.

This talk will present the latest open-source education activities at IHP, with a particular focus on the newly launched Open Source Chip Design Challenge, developed as part of the DI-OCDCpro project. This initiative introduces a competitive and hands-on training format aimed at students, career changers, and researchers, enabling them to complete a full open-source tapeout using real-world design flows. For the test run planned within the project, the challenge will use open-source EDA toolchains and target the IHP open-source SG13G2 technology. In addition to the challenge, the talk will briefly highlight the progress of the open-source EDA courses (digital and analog) developed within the FMD-QNC project at IHP. Following their first successful trial runs in early 2025, participant feedback has been largely integrated into the course content. All materials are openly licensed and made publicly available via Git repositories. The session will provide insights into the structure, motivation, and early outcomes of these initiatives, demonstrating how open-source tools and methodologies are being used to foster semiconductor education in Germany and beyond. This work is funded by the German Federal Ministry of Research, Technology and Space (BMFTR) as part of the DI-OCDCpro project (Funding Code: 16ME0940) and the FMD-QNC project (Funding Code: 16ME0831).

This talk describes the effort carried out to make our in-house Network-on-chip available to a wider commutity. To that end, the Network Interface (NI) was redesigned to support a broader range of communication protocols, including AXI-MM and AXI Stream. This effort targets a significant gap in open-source NoC architectures, where standard-compliant, reusable IP blocks are rarely available. By contributing these components as open-source, the project aims to improve accessibility and foster wider adoption and collaboration in the hardware research community.

BAFFI is an open-source FPGA fault injection (FFI) tool that automates dependability assessment of FPGA prototypes. It addresses some important limitations of existing FFI methodologies for the current generation of AMD devices, such as the coarse granularity of FI experiments and the lack of support for ASIC fault models. Like most modern FFI tools, BAFFI relies on the partial runtime reconfiguration (RTR) technique to emulate hardware faults. Additionally, BAFFI maps the configuration memory (CM) bits with the hierarchical design netlist for the main types of logic cells. This mapping enables targeting any selected component in the design tree for fault injection, either individual look-up tables (LUT) or registers, which provides finer-grain analysis capabilities than alternative tools and eliminates the need for area constraints. At the same time, BAFFI extends the set of fault models beyond the commonly considered single event upsets (SEU) in CM, to support the emulation of transient ASIC faults in the storage cells by orchestrating the manipulation of multiple associated CM bits. This talk provides further details on the architecture and capabilities of BAFFI and exemplifies its application to an open-source RISC-V SoC (NOELV) prototyped on an AMD Virtex Ultrascale+ FPGA.