(Tentative) This lighting talk demonstrates the programmability of the Simodense RISC-V softcore running on an FPGA. The latest extension of Simodense features runtime reconfigurability. The prototype is entirely written in Verilog and is thus applicable to a variety of scenarios including tape-out.

wafer.space provides budget silicon manufacturing for the GF180MCU process.

In this talk, we will take a look back at the wafer.space shuttle runs and the challenges that came with them. Furthermore, I will highlight a number of impressive open-source designs, as well as some very useful community-created IP. Finally, I will provide an outlook on ongoing and future developments.

OpenTestability is an open source DFT insertion tool for the open silicon ecosystem, handling scan chain stitching and test point insertion on Yosys-produced netlists. The tool addresses a gap in the open source DFT flow, where pattern generation and fault simulation tools exist but automated insertion of DFT structures has lacked a robust open implementation. This talk covers the insertion methodology, integration with downstream tools via standardized JSON interfaces, benchmarks on coverage impact across ISCAS and picorv32a, and the design choices that keep the tool retargetable across different scan architectures and technology libraries.

Every EDA tool reimplements its own LEF/DEF/GDSII/Tcl readers. rawast replaces them with one universal engine where the grammar is data — a runtime .rawast file, not compiled code. One engine parses any text or binary format into a queryable value tree, and because it’s bidirectional, the same grammar re-emits the text too. It’s self-hosting, GDSII is the worked binary example, and a planned container lets downstream tools parse once and never re-parse. The PoC parses a 3,132-file production corpus across four formats. C++17 + Python, MIT.

For a long time, one of the crucial items missing in the open silicon ecosystem has been a formal equivalence‑checking tool capable of verifying modern‑scale architectures. Kepler‑formal provides exactly that, with an advanced multi‑threaded C++ core that can handle even large designs in a timely fashion. This tool adds another important building block in the journey toward industrial‑level development with open‑source EDA. It has already been adopted publicly by several key players in the open silicon community and also saw usage in the industry. In this talk, we will present the tool and its use model, as well as our roadmap in terms of format support and features.

https://github.com/keplertech/kepler-formal

Packaged silicon parts have finally arrived on-site in time for summer 2026, including the second Chipalooza test chip on Sky130 and new 3.3V support for GF180MCU on the first Wafer.Space shuttle run. All circuits are functional! Characterization results will be presented for the several dozen analog blocks on the Chipalooza test chips as well as for the 3.3V SRAM and I/O library components. I will report on continuing efforts to provide open source analog libraries for all of the open PDKs.

Many questions about a hardware design are about connectivity: what drives this signal, what does it fan out to, is there a combinational loop, does this path cross a clock domain? Slang Netlist is an open-source C++ library that answers these by building a bit-level dependency graph directly over an elaborated SystemVerilog RTL design. Working at the source level rather than lowering to gates keeps close correspondence to the RTL and compilation fast; building on the slang front end brings rich SystemVerilog support and optimised parsing, elaboration, and data-flow analyses; and it is easy to integrate with Python bindings. This talk covers how it works — turning slang's analyses into a queryable graph — how to use it via the CLI and Python, and several use cases, including synthesis-style lint checks and clock-domain-crossing (CDC) analysis.

While building netlist tools at keplertech.io, we kept missing a lightweight schematic viewer for browsing design connectivity and hierarchy. naja-schematic has been an internal project we'd now like to open to the community for use and collaboration. It's a small, fast viewer in C++ leveraging Dear ImGui for portability and WebAssembly capabilities. It currently loads naja data structures, but we are looking for ways to offer a general way to load any data structure.

Where do the liberty files come from? How to create own liberty files with open source tools? This talk introduces OpenChar, a new open-source standard cell library characterizer. OpenChar uses NGSpice to simulate standard cells and generate liberty files and Verilog models for them. The talk will focus on user visible features and compare OpenChar with other existing open-source solutions. We briefly look at the internal workings of OpenChar, and since SW is never finished, we will also talk about missing features and future plans.