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Open source EDA for Machine Learning

At the Barcelona Supercomputing Center (BSC) we are actively pushing research on LLMs for chip design. Our early contributions include an integrated evaluation framework (TuRTLe) to assess RTL code quality under syntax, functionality, synthesizability and PPA performance. Commited to open science, this is done in integration with open tools (Icarus, Yosis, OpenROAD), and publicly released for others to use and extend. This talk will include insights on the latest model performance, evaluation challenges and future research lines of work, towards improving the use of LLMs for EDA.

HAgent is an open-source Hardware Agent infrastructure that integrates LLMs with chip design tools through a compiler-inspired pipeline architecture. The framework enables AI-assisted hardware development across with hermetic passes that communicate via YAML interfaces for enhanced debuggability and reproducibility.

B-ASIC is a work-in-progress open source framework for the design and implementation of static algorithms. Expressing an algorithm using a block diagram/signal flow graph, the algorithm can be simulated, including finite wordlengths. From that, the algorithm is mapped to hardware, by first scheduling the algorithm, extracting and mapping resources, resulting in an architecture. This can be done either manually, automatic or by a suitable combination, using the exact operations/processing elements that the designer finds suitable. A bit like high-level synthesis, but with more control of the steps. Finally, code describing major parts of the architecture can be generated.

APyTypes is a open source Python library, similar to NumPy, that provides fully parametrizable bit-exact scalar and array data types with either fixed-point or floating-point representation. This allows performing high-level simulations of finite word-length effect before implementing an algorithm. Implemented in C++, the library has significantly higher performance and/or are more complete than the alternatives. In this talk, APyTypes is introduced and it is shown how algorithms can be simulated and the results used for checking the implementation.

This talk briefly introduce the Surfer waveform viewer with a focus on recently added features and an outline of things that may be next.

The award-winning FuseSoC is now almost 15 years old and has become the most popular package manager for IP cores. There are today thousands of FuseSoC-compatible created and used by the industry, academia and hobbyists. One problem, however, has remained - where to find the IP cores.

To remedy this we have just introduced a project to build a public central database where users can browse and access IP cores, together with an easy way for users to make their own cores easily available for others.

This project proposes to create server-side infrastructure for a public collection of FuseSoC-compatible IP cores, a web interface to browse and inspect cores and expand FuseSoC to with code for users to easily publish their cores to this collection.

To improve trust in the system, and to help with CRA compliance, this project will also add support for signing packages, support for describing SPDX compliance and for applying tags to the project to indicate e.g. whether the project has been formally verified, silicon proven, is affected by any CVE, certifications etc.

A new approach in digital electronics design for FPGAs has recently arisen, featuring advanced packaging, versioning and dependency management capabilities for gateware HDL design. Strongly based on Guix dependency manager, this approach departs from traditional methods and opens the door to a fully declarative paradigm on dependency handling, including transactions and determinism, which guarantees traceability during the full design cycle. It is thus possible to treat IP Blocks as any other project requirement -including software-, in addition to producing fully reproducible environments and container images, facilitating the path towards modern continuous integration practices. User custom dedicated repositories allow the development of all that's necessary to build (hdlmake), simulate (ghdl), synthesize (yosys) and implement (nextpnr) designs remotely, using unit testing frameworks (vunit) and modern verification libraries (osvvm), in addition to performing cosimulation (cocotb) in remote forges.

In this talk we'll demonstrate a set of open source, vendor-agnostic tools allowing to automatically overview, document and analyze the digital design development and documentation process. For development and overview purposes we will cover such tools as topwrap for block design development and the PeakRDL source and documentation generator for registers. For verification and testing purposes we will cover the uvmdvgen tool for generating the base for UVM testbenches and verification, as well the testplanner and coverview tools for planning and tracking tests for digital design along with displaying the progress of implementation and code coverage. For simulation purposes we will demonstrate how the Renode (https://renode.io/) framework can be used for speeding up design testing. The entire suite will be demonstrated on a sample project, showing how the proposed tools can be combined to create a comprehensive overview of the design, its development and verification progress.

Let's look together at cocotb 2.0 and see what it has in store for all of us!

Junit outputs from cocotb are a useful building block for maintaining Continuous Integration (CI) for silicon projects. This can be extended through the use of OpenMetrics and Grafana to provide dashboards to present useful metrics and insights such as test coverage over time, simulator usage or bug tracking.

A follow up to our LatchUp 2024 verification with Verilator presentation. In this talk we'll show recent improvements in the steady progress towards UVM support that Antmicro and others have been contributing to over the years. We'll also cover related topics such as constrained randomization support, enhancements to coverage reporting, and improved facilities for power estimation workflows.

Constrainedrandom is a Python package for - you guessed it - creating and solving constrained randomization problems. It's faster than PyVSC. It achieves this by walking the through state space randomly, rather than using exhaustive solutions for constraints. That makes it much faster for the majority case, though it's possible for it not to converge for harder problems.

Overview of our open-source Transactron library for Amaranth HDL language, how it makes designing complex hardware easier, modular, solid and fun, introduction to the concept and demos.

Chisel is the award-winning hardware description language embedded in Scala for writing reusable hardware generators. While Chisel has existed for 15 years, I have been involved in development for the last 10. This talk is a bit of a retrospective on the last decade and a look toward the future.

At ExpectedIT, we develop IP for AI and scale-up servers in the datacenter. As young startup company, we chose to use open-source EDA tools for chip development. One of our designs implements a high-performance cache directory, for orchestrating cache coherency in a multi-CPU system.

We show our front-end design process, and share our RTL design and verification experiences so far. As minor contribution, we propose some enhancements to Chisel that helped us improve our code quality.

SystemVerilog Assertions are extensively utilized in the industry for the verification of silicon designs. However, support in open-source tools for this is limited. With the advent of CIRCT and the growing support for SystemVerilog, it is imperative to explore ways to extend this support to establish a more comprehensive verification system capable of handling concurrent assertions.

The Slang Language Server is a new tool built on top of Slang, the fastest and most compliant SystemVerilog frontend. Our goal is to provide a language server that is just as fast and accurate. This server offers a range of powerful features to accelerate your development in VSCode or Neovim. Here's what you can expect from the talk:

Getting Started: We'll begin by showing you how to set up and use the server, and how to customize it for your repo

HDL Features: We’ll showcase the hdl-specific protocol extensions like an elaborated hierarchy view and integrations with waveform viewers like Surfer.

Future Plans: Learn about what's next for the project

yosys-slang is a free and open extension for Yosys adding support for SystemVerilog design input. It has been used in two tapeouts and is seeing growing adoption in the community. The talk will cover the tool's status, future plans, and opportunities for other tools to build on top of its codebase.

Dyno-SV is a new open-source RTL synthesis tool. It is not based on either Yosys or MLIR, but Dyno-IR, a new generic IR for hardware and more. Dyno-IR enables representation of designs at every level of abstraction from behavioral to gate level, with sufficient performance for transformations, even at lower levels.

The tool is built around a middle end optimizer operating at the process/control flow level of abstraction. Only late is control flow fully discarded and code converted to netlist level. This approach allows using the middle end for both synthesis and simulation and simplifies a number of transformations.

The tool is in active development, already achieving end-to-end synthesis using Slang as a frontend and ABC as a combinatorial logic backend. We plan to further refine its capabilities as an extensible platform for hardware synthesis and simulation.

I present a Yosys plugin which connects the egglog equality saturation engine to Yosys, allowing Yosys users to easily insert their designs into an egraph, run rewrites over the egraph, and extract new versions of their design back into Yosys.

najaeda is a Python library that encapsulates naja, an advanced C++ open source framework for post synthesis netlist browsing and optimization. One of the prominent uses for najaeda by the community has been ECOs due to its ease of use, friendly API and installation. Licensed tools for ECOs can be costly and sometimes not dynamic enough. This results in a large number of engineers resorting to manual changes that can be time consuming and inconvenient. najaeda presents a reliable and straight forward open source alternative. In this talk we will do an overview of the library’s capabilities and our plan to integrate embedded verification infrastructure in order to meet industrial standards and provide the community with a fully open source alternative.

RV32I softcore and implementation from schematic to structural verilog (logilib) with verilator.

Systems that require low power consumption or high performance often employ in-hardware accelerators to meet these demands. While complex algorithms can be efficiently offloaded to memory-mapped accelerators, small computational kernels are typically unsuitable due to overhead and latency. For these cases, custom instructions provide a more efficient acceleration path. However, custom instructions introduce new challenges, including the need for tight integration into the processor pipeline, which can reduce portability.

Although tools for Instruction Set Architecture Extension (ISAX) integration exist, many are commercial, limited to specific core families (e.g., RoCC), support only a subset of instruction types (e.g., no memory access in CV-X-IF), or are still work-in-progress (e.g. RISC-V CX).

SCAIE-V overcomes these limitations by providing a flexible and efficient interface that integrates directly into the processor pipeline. Its logic generation framework supports portability across cores, simultaneous integration of multiple ISAXes, arbitrary instruction encodings, and stateful instruction behavior.

To support a wide range of use cases, SCAIE-V offers three instruction execution modes:

1. Tightly-coupled instructions execute in lockstep with the processor pipeline.
2. Semi-coupled instructions also execute in lockstep but may span multiple internal stages per pipeline stage, enabling more complex computations.
3. Decoupled instructions execute independently and may write back at any time, with hazards automatically managed by SCAIE-V.

In addition, SCAIE-V supports instruction-independent behavior, enabling operations that are decoupled from specific instruction execution, like zero-overhead loops.

SCAIE-V is compatible with several well-known RISC-V cores of varying complexity, such as PicoRV32, VexRiscv, CVA5, and CVA6. Implementation in a modern 22nm ASIC process demonstrates minimal overhead and significant performance gains.

In computer architecture courses, we usually teach RISC processors using a five-stage pipeline, neglecting alternative organizations. This design choice, rooted in 1980s technology, may not be optimal today, and it is certainly not the easiest pipeline for education. This talk examines more straightforward pipeline organizations for RISC processors suitable for educational purposes and for implementing embedded processors in FPGAs and ASICs. We analyze resource costs and maximum clock frequency of various designs implemented in an FPGA, using clock frequency as a performance proxy. Additionally, we validate these results with ASIC designs synthesized using the open-source SkyWater130 process.

Contradictory to common wisdom, a longer pipeline (up to 5 stages) does not necessarily always increase the maximum clock frequency. In two FPGA and one ASIC implementation, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor.

Open-source digital verification has advanced rapidly, but mixed-signal designs still lack a seamless path into modern RTL testbenches. This talk surveys today's community-driven options, pinpointing their remaining pain points.

I then introduce SpiceBind, a lightweight VPI bridge that embeds an ngspice solver inside any VPI-capable simulator. RTL and SPICE devices step on the same timestep, while your existing testbench, coverage, and waveform tools remain unchanged.

A top-level case study demonstrates how SpiceBind drops into a typical RTL simulation, and runs unmodified in a CI workflow.

Attendees will leave with an entirely open-source, reproducible recipe for bringing mixed-signal verification into their designed.

The design of advanced chips‚ especially in photonics, quantum, MEMS, and RF, faces critical challenges due to rigid, outdated EDA tools. Many teams resort to custom Python, C, or MATLAB solutions, which offer flexibility but lack scalability. To bridge this gap, we created GDSFactory, an open-source, python-based Analog Electronic Design Automation software that has been downloaded over 2 million times and adopted by companies, universities, and research organizations worldwide.

A FABulous FPGA utilizing the Panamax padframe designed using open source EDA tools and the open source sky130 PDK.

Panamax FPGA features 64 I/Os, 1280 LCs (LUT4+FF), 8 MAC (8-bit * 8-bit + 20-bit), 16 register files (1w2r, 32x4) and 8 BRAM (dual-ported 1r1rw, 256x32). In addition, the FPGA fabric integrates some analog IP: 2 x 12-bit split-CDAC SAR ADC and 2 x 8-bit R-DAC.

Panamax FPGA was submitted for tapeout in May 2025.

Let's take a look at the upcoming version 2.0 of the FABulous eFPGA Framework, which brings many new features and improvements.

FABulous is a user-friendly and yet highly customizable embedded FPGA (eFPGA) framework that covers all aspects of a complete eFPGA ecosystem. It has demonstrated good area density in both standard cell and custom cell based flows and supports extensive customization, including the integration of user-defined primitives, I/O cells, and complex blocks such as CPU cores or ADCs. The framework has been validated by more than ten manufactured chips, covering technology nodes from 28 nm to 180 nm. This demonstrates both its practicality and adaptability in a variety of design contexts.

For developing a SRAM compiler that is area efficient and performant expertise is needed but above all a lot transpiration and persistence; more so I would say than other circuits. Luckily we (e.g. ChipFlow) is developing one for IHP and their SG13G2 open source process. This work is done in the FlowSpace project funded by the German government. In this project, the Arrakeen python framework - presented at last years ORConf - is used so the resulting compiler will also be easily portable to other technologies. Porting to Sky130 and GF180MCU is in the planning. In the FlowSpace project, next to the compiler itself, extensions will be developed to radiation harden the resulting blocks.

In this presentation a little background will be given on SRAM compiler design followed by the current status of the compiler and the improvements done in the Arrakeen framework to make all this work possible.

DRAMSys is the go-to tool for developers and engineers who need full transparency in product development with integrated DRAM subsystems. This advanced open-source simulation framework, built on the SystemC TLM-2.0 standard, delivers unmatched flexibility and performance. DRAMSys follows a Freemium model, combining open-source accessibility with commercial options. The latest memory standards—such as DDR5, LPDDR5, and HBM3—are available through commercial models distributed by Fraunhofer IESE, with the revenue supporting ongoing maintenance and the development of future memory technologies. Universities can benefit from free academic licenses. DRAMSys is widely used in Industry, e.g. by Rambus and Ateris. With DRAMSys, you can tackle the complexities of modern memory systems effortlessly. Whether analyzing bandwidth, latency, or power consumption, DRAMSys equips you with the tools to optimize your design. This talk will provide insights and real-world use cases of DRAMSys in action. (DRAMSys is a project in the German Design Initiative.)

Designed to overcome the limitations of OpenLane but maintain its signature ease-of-configuration and ease-of-installation, LibreLane is the modular and extensible community-driven successor to the world's most popular open source EDA flow, reimagining it as not just a flow, but as a customizable ASIC data flow infrastructure. In this talk, we will outline what motivated us to make LibreLane, what it's currently capable of, and our future development plans, as well as a showcase of both simple and advanced use-cases it enables.

Achieving robust timing closure is paramount in modern ASIC design. This talk delves into the critical role of physical synthesis and timing optimization within the OpenROAD flow, with a particular focus on its powerful Resizer module. This presentation will highlight the significant recent advancements and capabilities integrated into OpenROAD's Resizer. We will explore how these updates enhance its ability to perform sophisticated gate sizing, buffer insertion, and netlist restructuring, leading to improved power, performance, and area (PPA) metrics. Attendees will gain practical insights into effectively constraining their designs and harnessing the latest features of the OpenROAD Resizer to achieve superior timing closure results for their open-source hardware projects.

Prof. Guthaus also wants to meet up with others on Sunday to discuss timing closure challenges on your open-source projects.

Space electronics operate in an environment that demands the highest levels of reliability, radiation tolerance, and performance - under some of the harshest constraints on Size, Weight & Power (SWaP). Yet system designers are consistently faced with a painful choice: use off-the-shelf terrestrial chips that aren’t built for the mission, or rely on space-rated parts that are expensive, obsolete, and lacking performance.

At SPHERICAL, we’re solving this problem by collapsing the gap between chips and systems. We build high-reliability, high-performance space systems by designing our own mission-specific chips - enabled by open-source tools and a modern, software-first methodology. This approach lets us deliver systems that are not only more capable but radically more flexible, auditable, and scalable.

This talk will walk through our design philosophy, the tool flows we’ve developed and adapted, and how we’re leveraging the open-source silicon ecosystem to deliver 10x improvements in performance, reliability, and configurability. We’ll close by reflecting on the opportunities and missing pieces for the open-source community to power the next generation of critical systems.

Based on experience of guiding engineering at a silicon startup using FOSS tools and a strategy of open sourcing where possible, this presentation will explore where that limit is today, lessons learnt from this strategy, and some tips for others considering such an approach.

The Microelectronics Systems Group at Sheffield University has been running multiple experiments over the last three years in how to embed Chip Design into a workforce development program including undergraduate and masters curriculum and student outreach. Aligning with national skills initiatives, getting funding for a sustainable program, dealing with learning outcomes, accreditation, dealing with the commerical ecosystem are all fun topics - beyond the technical. What drove us to use open source - to trial certain open source platforms and assets, what were our experiences, where are the gaps, and how do we move forward?

This is the third time I have tried to deliver this presentation having been thwarted by travel to both OrConf24 and Latchup25 hopefully the travel gods will smile on me. I will provide a quick update on the UK national zeitgeist in Semiconductors as part of this talk which may be of interest to the room - you will be happy that Open Srouce is a key feature of our Skills and Design Platform Initiative.

This talk will present the latest open-source education activities at IHP, with a particular focus on the newly launched Open Source Chip Design Challenge, developed as part of the DI-OCDCpro project. This initiative introduces a competitive and hands-on training format aimed at students, career changers, and researchers, enabling them to complete a full open-source tapeout using real-world design flows. For the test run planned within the project, the challenge will use open-source EDA toolchains and target the IHP open-source SG13G2 technology. In addition to the challenge, the talk will briefly highlight the progress of the open-source EDA courses (digital and analog) developed within the FMD-QNC project at IHP. Following their first successful trial runs in early 2025, participant feedback has been largely integrated into the course content. All materials are openly licensed and made publicly available via Git repositories. The session will provide insights into the structure, motivation, and early outcomes of these initiatives, demonstrating how open-source tools and methodologies are being used to foster semiconductor education in Germany and beyond. This work is funded by the German Federal Ministry of Research, Technology and Space (BMFTR) as part of the DI-OCDCpro project (Funding Code: 16ME0940) and the FMD-QNC project (Funding Code: 16ME0831).

This presentation will provide a brief overview of the EuroCDP (European Chip Design Platform), with a special focus on its open branch. The talk will highlight the key components available to the community, including an Open Source Software (OSS) toolbox for Level 0 users and an OSS sandbox environment for Level 1 and Level 2 users. The platform is designed to empower a broad range of stakeholders by enabling access to open EDA tools and an open IP catalog, all within a transparent and collaborative framework.

In this talk, we’ll share the story of how three engineers launched a semiconductor startup—ChipFoundry.io—in just six weeks, thanks to the open-source silicon ecosystem. With zero proprietary EDA licenses and no upfront IP costs, we built a real business around accessible, reproducible chip design.

We’ll highlight how tools like OpenLane, the Sky130 PDK, the Caravel SoC template, and open IP libraries allowed us to go from concept to a working ASIC flow within weeks. We’ll also cover what worked, what didn’t, and how the vibrant community helped us overcome blockers that would’ve stalled a conventional startup for months.

This is a talk about speed, leverage, and the power of open collaboration in a space once reserved for giants.

Sesenta: Open source FPGA based tileable acoustic camera sesenta is a tool for creation of acoustic cameras. has a modular design. It consists of 2 parts: the microphone array and FPGA based control boards. Each array is a board with a lattice of 60 microphones designed to work in conjunction with other arrays (tile of arrays). A Sesenta can work independently, but the ability to use it as a tile allows for an expanded range.

Tiliqua is an open hardware development platform, DSP library and collection of examples (built in Amaranth HDL) that aims to make FPGA-based audio and video synthesis more accessible. This talk builds on last year's edition, this time covering some war stories from the past 12 months of getting Tiliqua hardware ready to ship, and all the new features added to the DSP/RTL library since then. We'll cover some fun topics such:

• Implementing low-latency USB host purely in gateware
• Dynamic frequency scaling for display switching
• New DSP cores and example projects
• How we are adding first-class fixed-point types to the Amaranth language
• Lessons learned from shipping hardware (and some tricks for passing CE/EMC)

As we walk through each theme, this talk will include some live demos on a small Eurorack system demonstrating each.

WIP

We demonstrate how we can use LLMs to develop a deep understanding of complex designs via simple iterative experimentation.

Bamlet is a VLIW SIMT processor designed to be used in a many-core accelerator mesh. Written in Chisel, tested with cocotb and PPA using OpenROAD-flow-scripts.

Jetbrains MPS is a powerful open source framework for defining and entering single source data using custom DSLs (Domain Specific Languages). This presentation shows how it can be used to capture machine-readable single source data on all levels of abstractions: to model architecture, to define configurations their constraints, collect targeted product variants down to the description of HSI (SFR/CSR) in a System RDL style.

This presentation will address:

1. Motivations regarding security within the German research projects HEP and Sign-HEP. These projects are about creating open security modules with an open tool chain and PDK. Any potential attacks from insiders or outsiders need to be taken into account. If properly addressed, the approach will allow confidential communication, secure boot, code-signing, etc. The presentation will furthermore introduce two new documents concerning plans for action, namely:
2. High-level specifications about how to design a Caliptra-like security module, with an emphasis on open components without vulnerabilities. The specification is planned to be made available ahead of the conference. It contains information about our plans to design an open, hardware-based random number generator. Furthermore, an extension to the IHP-Open130-G2 PDK will be provided, i.e. root of trust elements as a proprietary, certifiable module, usable for industrial adoption, with free access to academia. We encourage industry to express interest in our approach, experts to comment, and media to report about the planned open security module design.
3. Furthermore, a Working Paper will be presented describing paths for open- source hardware. The paper addresses issues such as a) already emerging products, b) easing innovation, c) issues of global co-ordination and 4) paths towards more efficient, more open and more secure fabs. The paper is already available at https://hep-alliance.org/Project/.

This talk describes the effort carried out to make our in-house Network-on-chip available to a wider commutity. To that end, the Network Interface (NI) was redesigned to support a broader range of communication protocols, including AXI-MM and AXI Stream. This effort targets a significant gap in open-source NoC architectures, where standard-compliant, reusable IP blocks are rarely available. By contributing these components as open-source, the project aims to improve accessibility and foster wider adoption and collaboration in the hardware research community.

BAFFI is an open-source FPGA fault injection (FFI) tool that automates dependability assessment of FPGA prototypes. It addresses some important limitations of existing FFI methodologies for the current generation of AMD devices, such as the coarse granularity of FI experiments and the lack of support for ASIC fault models. Like most modern FFI tools, BAFFI relies on the partial runtime reconfiguration (RTR) technique to emulate hardware faults. Additionally, BAFFI maps the configuration memory (CM) bits with the hierarchical design netlist for the main types of logic cells. This mapping enables targeting any selected component in the design tree for fault injection, either individual look-up tables (LUT) or registers, which provides finer-grain analysis capabilities than alternative tools and eliminates the need for area constraints. At the same time, BAFFI extends the set of fault models beyond the commonly considered single event upsets (SEU) in CM, to support the emulation of transient ASIC faults in the storage cells by orchestrating the manipulation of multiple associated CM bits. This talk provides further details on the architecture and capabilities of BAFFI and exemplifies its application to an open-source RISC-V SoC (NOELV) prototyped on an AMD Virtex Ultrascale+ FPGA.