The fact that all the computers and switches in a data center are mostly independent and asynchronously operating entities can cause issues. This includes a wide variance in end-to-end latency (“lag spike”), to efficient compute resource usage; and on top of that: all the buffers that are all over the place are consuming a lot of energy. Imagine, however, what would happen if you could treat your entire data center as a synchronous digital circuit: latency becomes deterministic, scheduling applications for efficient resource usage becomes easier, and you can drastically reduce buffer sizes. This is what the Bittide project, aims to achieve: to bring ‘logical’ synchrony to data centers. This talk will explain what ‘logical’ synchrony is and how we used Clash, to build the hardware support to enable it.

https://github.com/ucb-bar/saturn-vectors

The VexiiRiscv (Vex2Risc5) project aim at replacing VexRiscv and extends its scope with features such as multi-issue, hardware prefetcher, 64 bits support, ... This presentation will mainly be a live demonstration of the project running Debian on FPGA, exposing the level of performance achievable on such system including boot, userland, some demos and finaly a few slides.

FazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial, 2-, 4-, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by, e.g., avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales, answer why there is no 16-bit variant, discuss how the performance can be improved, and outline possible extensions to improve the current FazyRV design.

PunyCC is a cross compiler for a very small subset of C. Only one source file, no preprocessor, no structs, no floating point and only one datatype that can be used as unsigend int or pointer to char. Due to these simplifications the compiler source code is very small and can easily be adopted to a new target instruction set. So far PunyCC supported 4 architectures: ARM Thumb-2, RISC-V, x86-32 and WebAssembly. It can compile itself and thus provides cross compilers from any of the instruction sets to any other. This talk presents how easy it is to add OpenRISC support to PunyCC. Use it as a blueprint for porting PunyCC to your own special instruction set.

Open source silicon and open source EDA tools have been identified as strategically important for European sovereignty. The GoIT! project and FOSSi Foundation have been tasked with creating a roadmap and recommendations for open source EDA in Europe. In this presentation, we will give an overview about the roadmap and initiate the community feedback period, which is extremely important for the success of the roadmap.

CHIPS Alliance’s open source Caliptra Root of Trust Project (a collaboration between AMD, Google, Microsoft and NVIDIA) is heading towards a 2.0 release. This talk will cover recent open source developments resulting from Antmicro’s involvement in the project, expanding on last year’s update at ORConf: a new open source I3C core built for use in future Caliptra integrations, further developments in the RISC-V-based VeeR core including PMP, ePMP and User Mode support, fully open verification of the AXI bus interface with Verilator and axi-vip verification IP and a number of improvements related to coverage visualization, automated documentation and chip aggregation. The talk will also present the SystemRDL integration with Renode speeding up generation of the co-simulation verification environment, as well as Caliptra’s entry in Antmicro’s System Designer which lets you explore the SoC’s structure, RTL and verification artifacts from a block diagram perspective.

While individual projects like Linux and GCC paved the road for open source software success, it can be argued that the thing that really enabled scaling up development of Linux-based solutions was the idea of package management. Having a common way to install software and describe their relations made it possible to rapidly create custom systems. The same can be said for language-specific package managers like pip for Python or Cargo for Rust.

On the chip design side, FuseSoC has been doing the same thing since its inception 2011. It is by now likely the world's most widely used package manager, both for open source projects and for proprietary code.

The background of FuseSoC has been presented several times over the years, so this presentation aims to instead look ahead and see what new features that are in store for FuseSoC and its sister project Edalize.

Surfer is a new waveform viewer focused on extensibility and a snappy interface. This presentation will briefly show off Surfer, showcase off how an extensible waveform viewer can be used for more effective debugging such as translating types from high level HDLs, visualising the results of waveform analysis, or even as a teaching tool. The presentation will also showcase some recently added features such as transaction visualization, the "Surver" headless interface, and scriptable plugins.

APyTypes is an array library for Python with highly configurable bit-accurate fixed-point and floating-point data types of arbitrary word length written in C++. Hence, it can be used to easily simulate finite word length effects and to provide reference data for hardware implementations. This talk discuss features of APyTypes, how to work with it, and how it compares against other libraries with a similar purpose.

This talk will present the ongoing effort and progress in creating the OS-EDA course. An overview of the available materials, lectures, and hands-on components will be included. Additionally, we will explain how to participate and use the materials independently. A first test run of the course, planned to be held in-house at IHP, will be announced during this talk at ORConf. The course's overall goal is to help participants understand and use open-source EDA tools to create an open-source tapeout, with IHP as the default target chip factory and the usage of OPENROAD. The course will be available in English, with all materials hosted in a public Git repository under an open-source license. This work is funded by the German Federal Ministry of Education and Research in the Project FMD-QNC (16ME0831).This talk will present the development of certificate courses within the FMD-QNC project, which will be part of an educational platform aimed at training individuals from trainees to academics. The OS-EDA courses under development at IHP target academics and career changers. We will present the progress in creating the digital OS-EDA course, including an overview of the available materials, lectures, and hands-on components. Additionally, we will explain how to participate and use the materials independently.

A first test run of the course, planned to be held in-house at IHP, will be announced during this talk at ORConf. The overall goal of the course is to help participants understand and use open-source EDA tools to create an open-source tapeout, with IHP as the default target chip factory and the use of OPENROAD.

The course will be available in English, with all materials hosted in a public Git repository under an open-source license. This work is funded by the German Federal Ministry of Education and Research as part of the FMD-QNC project (16ME0831).

Design and development process of the "Drop" demo for the TinyTapeout Demoscene 2024 competition. The dedicated ASIC is a self contained 150x220 um piece of silicon built on a 130 nm process, requires no CPU, GPU or external memory and produces VGA signal in a "racing the beam" fashion. The talk will cover tools and hardware used during the development of the demo. Optimisation techniques to fit multiple graphical effects into extremely tight area of 150x220 um and quick comparison of the dedicated ASIC design vs "classical" chips for graphics and audio synthesis.

Analog microelectronics is a crucial but often overlooked part of ASIC design. In this talk I will share my experience getting started with analog microelectronics, and taping out my first few designs. I will cover motivation, tools, my designs, and my success and failures so far. The presentation will end with a discussion on how this fascinating topic fits into the wider picture of open source silicon and the next steps needed to enable radio transmitters and receivers.

With the avenue of AI as a game changer, what would Open Source Standard Cell Library Design consist in to date? Where to start ? Let's focus on combinatorics to provide with an unexpected contribution.

Project Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells, IO cells, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it's subprojects for the three supported open source PDKs, e.g. Sky130, IHP SG13G2 and GF180MCU will be presented.

Open-source tools for ASIC design are gaining momentum due to their cost-effectiveness, customizability, and reliability. These tools have proven their value through multiple successful designs in recent years. This talk will present our experience in successfully porting a proprietary 110nm Process Design Kit (PDK) to open-source EDA tools such as Yosys and OpenRoad. We will discuss both the successes and challenges encountered during this process, using the prototype Gbit serial data link as a case study.

Join us for a dive into DFHDL (DFiant Hardware Description Language), where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF), Register-Transfer (RT), and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works, why it matters, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP)

SystemVerilog and UVM have dominated digital verification, even though they are relatively old technologies with significant limitations. The EDA industry's strategy has been to develop smarter (and more expensive) tools based on these technologies. However, Cocotb offers a different approach. It minimizes the reliance on EDA tools (limited to just simulation) by enabling the vast capabilities of the Python ecosystem.

Is this a recipe for success? What challenges does it present? Is there room for both strategies in the future?

In this presentation, I will discuss some general considerations, as well as share experiences from successful deployments of the Cocotb flow in industrial projects (which might even be in your pocket right now).

Some fancy around-Cocotb ideas developed will be shown: usage of massive parallelism, flow unification with algorithm-level modeling and checkpointing.

Since it's inception and the minting of 1.0, cocotb has carried with it several design issues that only API-breaking changes could fix. 2024 is the year those issues finally get fixed. cocotb 2.0 includes changes to how tests are parameterized and selected, how tasks are managed, how HDL values are represented in Python, and how simulations are run. Tune in to this talk to learn how to leverage these new features and how to make your code 2.0 compliant.

Forastero is a Python library that builds on top of cocotb adding standard components like drivers, monitors, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I'll present how you can use Forastero to quickly construct a testbench around a DUT, driving and monitoring multiple interfaces, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero

Bucket is a python-based functional coverage tool designed to work easily with cocotb(/Forastero). It allows for the easy creation of multiple nested covergroups and coverpoints with a straight forward sampling mechanism. Each coverpoint is a cross of one or more axes, with the ability to modify target hits, illegal or ignore status for each bucket. The data to be covered can be sampled directly from the DUT, higher levels of abstraction (such as entire CPU pipelines), or even parsing of logs/test output. Bucket is being actively developed and used by Vypercore for our own IP. It is fully open source and available at github.com/VyperCore/bucket, where you can find further documentation and examples.

UVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming, below are some of the sample lint rules that are relevant to the UVM BCL codebase:

• Avoid race condition around "static const" (use localparam instead)
• Avoid one-liner conditional statements:
  • if (cond) $display ("cond");
  • if (cond) .. else $display ("Else cond as single line");
  • case..endcase
• Avoid one-liner code in loops: for, repeat, while, do..while, foreach
• Use endlabels for elements such as endclass, endfunction, endtask etc.
• Flag non-virtual methods

Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase.

The Renode simulation framework is being used in a number of projects and open source initiatives developing new ASIC-targeted IPs and SoCs. It lets you mix fast, functional full-system simulation with co-simulated RTL blocks. This talk will show how Renode's DPI interface support allows interfacing SystemVerilog IP simulated with Verilator or other DPI-capable simulators via a range of bus interfaces as well as present the newly-added SystemC TLM support. Renode's co-simulation capabilities together with features like trace-based modeling as well as flexible support of the RISC-V ISA including simple definition of custom instructions, help explore architectural choices, analyze the security and performance of in-development SoCs, develop software pre-silicon, and build rigorous, deterministic test suites which guide teams through the entire development lifecycle of SoCs.

Tiliqua is an open hardware development platform, DSP library and collection of examples (built in Amaranth HDL) that aims to make FPGA-based audio and video synthesis more accessible. The hardware itself is designed to integrate into the Eurorack ecosystem, or can be easily taken apart and used in custom instrument designs. This presentation will go through the Tiliqua hardware design, the RTL framework provided and some of the included example projects. The project is distributed under CERN-OHL-S-V2 and is under active development here: https://github.com/apfelaudio/tiliqua

The RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall, FireSim facilitates faster iteration cycles and informed design decisions, benefiting individual developers and fostering collaboration in remote teams.

Digital signal processing (DSP) paths are usually simulated at a high level using C or MATLAB/Simulink models to confirm basic functionality and to assess whether signal processing requirements such as frequency response and signal-to-noise ratio are being met. Complex signal processing paths consist of cascades of sigma-delta modulators, filter stages, mixers, modulators, demodulators etc each of which have a corresponding high level model. A very simple framework has been developed in Julia to enable combinations of DSP stages to be evaluated. This talk will discuss the experience of using Julia to combine models written in Julia and C, and designs written in Verilog (using Verilator) in industrial settings over many years. The principles should also be applicable to C++ or Python evaluation environments.

OSVVM is a suite of libraries designed to streamline your VHDL entire verification process, boosting productivity and reducing development time. Each library provides independent capabilities, allowing selective adoption and a learn-as-you-go approach. Whether using directed or random testing, OSVVM facilitates writing concise and readable test cases for both simple unit/RTL tests and complex, full-chip or system-level FPGA and ASIC tests. OSVVM provides VHDL with verification capabilities that rival SystemVerilog + UVM. These include transaction-level modeling, verification components, co-simulation with software, randomized test generation, self-checking test support, verification data structures, comprehensive test reporting in HTML and text, and synchronization primitives. With OSVVM and a good team lead, any VHDL engineer can do verification – and have fun doing it. OSVVM grew rapidly during the COVID years, giving us better capability, better data structures, better test reporting (HTML and Junit), and scripting that is simple to use (and works with most VHDL simulators). This presentation will show how these advances fit into the overall OSVVM Methodology.

BenchBot is an open-source Python based app developed to automate the generation of OSVVM-compliant testbenches for VHDL designs. It utilizes YAML configuration files to define testbench parameters, enabling users to quickly produce tailored test environments for their DUTs. Main goal of this bot is to provide a ready-to-use OSVMM compliant testbench for a given VHDL DUT with popular elements such as clock generator, reset generator, main stimulus place holder, a watchdog etc. It also paves way to distributed test development by leveraging on modular testbench architecture using OSVMM framework. In this paper, we share our experience of using BenchBot on various open-source VHDL designs available online for the community, ensuring its reliability and versatility across different use cases. Along the way, we found a few unsupported constructs and added enhancements to the bot. This bot streamlines the process of creating standardized testbenches, making integrating it into existing VHDL development workflows easier.

Interpreters are very helpful tools for hardware development, but most existing tools require lots of memory, or slow interprocess communication. Best to use a tiny open source interpreter that runs on both the FPGA, and in the simulator, without any interprocess communication. The Mecrisp Ice soft core includes such an interpreter. 2K cross compiled words of memory (4K Bytes) required for the nucleus. On ICE 40 FPGAs, most people use 5K words for the entire system, plus 3K for their own application. Smaller applications are also possible. Using the interpreter for debugging, an 88 word compute kernel was built for loading SPRAM from FLASH. Applications requiring more data memory are also possible.

naja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination, Constant Propagation, and Primitives Optimization, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs.