A new approach in digital electronics design for FPGAs has recently arisen, featuring advanced packaging, versioning and dependency management capabilities for gateware HDL design. Strongly based on Guix dependency manager, this approach departs from traditional methods and opens the door to a fully declarative paradigm on dependency handling, including transactions and determinism, which guarantees traceability during the full design cycle. It is thus possible to treat IP Blocks as any other project requirement -including software-, in addition to producing fully reproducible environments and container images, facilitating the path towards modern continuous integration practices. User custom dedicated repositories allow the development of all that's necessary to build (hdlmake), simulate (ghdl), and synthesize (yosys) designs remotely, using unit testing frameworks (vunit) and modern verification libraries (osvvm), in addition to performing cosimulation (cocotb) in remote forges.

The design of advanced chips‚ especially in photonics, quantum, MEMS, and RF, faces critical challenges due to rigid, outdated EDA tools. Many teams resort to custom Python, C, or MATLAB solutions, which offer flexibility but lack scalability. To bridge this gap, we created GDSFactory, an open-source, python-based Analog Electronic Design Automation software that has been downloaded over 2 million times and adopted by companies, universities, and research organizations worldwide.

Tiliqua is an open hardware development platform, DSP library and collection of examples (built in Amaranth HDL) that aims to make FPGA-based audio and video synthesis more accessible. This talk builds on last year's edition, this time covering some war stories from the past 12 months of getting Tiliqua hardware ready to ship, and all the new features added to the DSP/RTL library since then. We'll cover some fun topics such:

• Implementing low-latency USB host purely in gateware
• Dynamic frequency scaling for display switching
• New DSP cores and example projects
• How we are adding first-class fixed-point types to the Amaranth language
• Lessons learned from shipping hardware (and some tricks for passing CE/EMC)

As we walk through each theme, this talk will include some live demos on a small Eurorack system demonstrating each.

A FABulous FPGA utilizing the Panamax padframe designed using open source EDA tools and the open source sky130 PDK.

Panamax FPGA features 64 I/Os, 1280 LCs (LUT4+FF), 8 MAC (8-bit * 8-bit + 20-bit), 16 register files (1w2r, 32x4) and 8 BRAM (dual-ported 1r1rw, 256x32). In addition, the FPGA fabric integrates some analog IP: 2 x 12-bit split-CDAC SAR ADC and 2 x 8-bit R-DAC.

Panamax FPGA was submitted for tapeout in May 2025.

At the Barcelona Supercomputing Center (BSC) we are actively pushing research on LLMs for chip design. Our early contributions include an integrated evaluation framework (TuRTLe) to assess RTL code quality under syntax, functionality, synthesizability and PPA performance. Commited to open science, this is done in integration with open tools (Icarus, Yosis, OpenROAD), and publicly released for others to use and extend. This talk will include insights on the latest model performance, evaluation challenges and future research lines of work, towards improving the use of LLMs for EDA.

HAgent is an open-source Hardware Agent infrastructure that integrates LLMs with chip design tools through a compiler-inspired pipeline architecture. The framework enables AI-assisted hardware development across with hermetic passes that communicate via YAML interfaces for enhanced debuggability and reproducibility.

Based on experience of guiding engineering at a silicon startup using FOSS tools and a strategy of open sourcing where possible, this presentation will explore where that limit is today, lessons learnt from this strategy, and some tips for others considering such an approach.

Constrainedrandom is a Python package for - you guessed it - creating and solving constrained randomization problems. It's faster than PyVSC. It achieves this by walking the through state space randomly, rather than using exhaustive solutions for constraints. That makes it much faster for the majority case, though it's possible for it not to converge for harder problems.

Overview of our open-source Transactron library for Amaranth HDL language, how it makes designing complex hardware easier, modular, solid and fun, introduction to the concept and demos.

Designed to overcome the limitations of OpenLane but maintain its signature ease-of-configuration and ease-of-installation, LibreLane is the modular and extensible community-driven successor to the world's most popular open source EDA flow, reimagining it as not just a flow, but as a customizable ASIC data flow infrastructure. In this talk, we will outline what motivated us to make LibreLane, what it's currently capable of, and our future development plans, as well as a showcase of both simple and advanced use-cases it enables.

In computer architecture courses, we usually teach RISC processors using a five-stage pipeline, neglecting alternative organizations. This design choice, rooted in 1980s technology, may not be optimal today, and it is certainly not the easiest pipeline for education. This talk examines more straightforward pipeline organizations for RISC processors suitable for educational purposes and for implementing embedded processors in FPGAs and ASICs. We analyze resource costs and maximum clock frequency of various designs implemented in an FPGA, using clock frequency as a performance proxy. Additionally, we validate these results with ASIC designs synthesized using the open-source SkyWater130 process.

Contradictory to common wisdom, a longer pipeline (up to 5 stages) does not necessarily always increase the maximum clock frequency. In two FPGA and one ASIC implementation, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor.

Open-source digital verification has advanced rapidly, but mixed-signal designs still lack a seamless path into modern RTL testbenches. This talk surveys today's community-driven options, pinpointing their remaining pain points.

I then introduce SpiceBind, a lightweight VPI bridge that embeds an ngspice solver inside any VPI-capable simulator. RTL and SPICE devices step on the same timestep, while your existing testbench, coverage, and waveform tools remain unchanged.

A top-level case study demonstrates how SpiceBind drops into a typical RTL simulation, and runs unmodified in a CI workflow.

Attendees will leave with an entirely open-source, reproducible recipe for bringing mixed-signal verification into their designed.

Junit outputs from cocotb are a useful building block for maintaining Continuous Integration (CI) for silicon projects. This can be extended through the use of OpenMetrics and Grafana to provide dashboards to present useful metrics and insights such as test coverage over time, simulator usage or bug tracking.

"yosys-slang" is a free and open extension for Yosys adding support for SystemVerilog design input. It has been used in two tapeouts and is seeing growing adoption in the community. The talk will cover the tool's status, future plans, and opportunities for other tools to build on top of its codebase.

RV32I softcore and implementation from schematic to structural verilog (logilib) with verilator.