Chat

Chat with fellow ORConf attendees in our Matrix chat room at #orconf2024:fossi-foundation.org. Any Matrix client works, or just use the Element web chat.

Submit a talk

Presentation submissions are made through the Eventbrite registration interface.

Please make your submissions as early as you can, as the presentation slots are likely to fill up at ORConf this year.

Code of conduct

We ask all ORConf participants to adhere to the the FOSSi Foundation code of conduct throughout the event.

Sponsors

A variety of sponsorship packages are available for this year's ORConf. You'll find all of the details in our sponsorship prospectus.

Please get in touch via email to explore the opportunities: orconf@fossi-foundation.org.

Venue

Gothenburg, Sweden.

Precise venue details TBD, but it will be relatively central to town.

Schedule

The detailed schedule will be available once we have all of the presentation submissions.

Friday

Presentations from about mid-morning.

Saturday

Presentations all day, conference event Saturday evening.

Sunday

Presentations and workshops until midday/early afternoon.

Programme

Please submit your presentation proposals when registering via the Eventbrite page.

Preliminary programme. More to come later.

Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study

Marek Pikuła

The RISC-V Vector Extension (RVV) promises an enhanced performance and power efficiency across various complex computational tasks. However, the efficient utilization of RVV demands careful consideration of the optimization approach. This article examines strategies for accelerating this process. Key challenges include assessing performance differences among algorithmic approaches and overcoming initial hardware constraints. FireSim provides a comprehensive solution by offering advanced software and hardware simulation capabilities. Utilizing FireSim, we started the process of enhancing source code with RVV instructions (called vectorization) for the pixman project. Our experience outlines the efficacy of a cloud-based FPGA simulation in expediting software development for emerging ISA extensions. Overall, FireSim facilitates faster iteration cycles and informed design decisions, benefiting individual developers and fostering collaboration in remote teams.

FazyRV: A RISC-V Core that Scales to Your Needs

Meinhard Kissich

FazyRV is a scalable RISC-V core that can be synthesized into a (1-)bit-serial, 2-, 4-, or 8-bit-serial implementation to fulfill your performance requirements with the least area (resp. resources) demand. FazyRV provides manifold variants to adapt to the target technology by, e.g., avoiding dual-port BRAM at the cost of an additional clock cycle. Contradictory to hand-optimized cores at the gate level, FazyRV tries to avoid manual low-level optimizations to increase readability and simplify adaptations. This talk gives an insight into the open-source FazyRV core and its design objectives. We show how the area demand scales, answer why there is no 16-bit variant, discuss how the performance can be improved, and outline possible extensions to improve the current FazyRV design.

Understanding and Supporting Open Source Silicon Communities

Stefan Wallentowitz

TBD

Debug your Design with a Tiny Interpreter

Christopher Lozinski

Interpreters are very helpful tools for hardware development, but the existing tools require slow interprocess communication, and lots of memory. Best to use a tiny interpreter that runs on both the FPGA, and in the simulator. . Less than 2KBytes of memory required and there is no slow interprocess communication. There are even two ASICs that run similar interpreters. .

VexiiRiscv : A Debian demonstration

Charles Papon

The VexiiRiscv (Vex2Risc5) project aim at remplacing VexRiscv and extends its scope with features such as multi-issue, hardware prefetcher, 64 bits support, ... This presentation will mainly be a live demonstration of the project running Debian on FPGA, exposing the level of performance achievable on such system including boot, userland, some demos and finaly a few slides.

Project Arrakeen: One API to rule all PDKs

Staf Verhaegen

Project Arrakeen is an umbrella project for providing a python framework for portable and scalable digital and analog circuits. It is based on the PDKMaster base project which provide a uniform API to PDK data and generation of circuit and layouts. On this base project other projects are being built that provide standard cells, IO cells, SRAM compiler and analog blocks. In this talk the state of the Arrakeen project and it's subprojects for the three supported open source PDKs, e.g. Sky130, IHP SG13G2 and GF180MCU will be presented.

naja_edit: An Open Source Tool for Gate-Level Netlist editing and optimization

Christophe Alexandre

naja_edit is an open source tool designed to optimize and edit gate-level netlists. It features algorithms for Dead Logic Elimination, Constant Propagation, and Primitives Optimization, all performed with minimal changes to the hierarchical netlist structure. This tool can be interleaved with Yosys and OpenROAD, making it particularly useful for large designs requiring hierarchical synthesis. naja_edit also features a Python interface for power users to inspect and edit the netlist using simple scripts. This talk will present optimization results on a set of open source designs.

Forastero: cocotb testbenches with batteries included

Peter Birch

Forastero is a Python library that builds on top of cocotb adding standard components like drivers, monitors, and scoreboards but without bringing the full weight of a UVM environment. While in some ways a spiritual successor to cocotb-bus, Forastero goes further and provides mechanisms for generating complex random stimulus. In this talk I'll present how you can use Forastero to quickly construct a testbench around a DUT, driving and monitoring multiple interfaces, and producing complex stimulus patterns. Forastero is fully open source and comes with both documentation and examples. It can be found on GitHub at github.com/Intuity/forastero

DFHDL: The 3-in-1 Abstraction Approach to Hardware Design

Oron Port

Join us for a dive into DFHDL (DFiant Hardware Description Language), where we break down a fresh approach to hardware design. This talk introduces a unique three-layer abstraction method that blends Dataflow (DF), Register-Transfer (RT), and Event-Driven (ED) models into one streamlined framework. We’ll explore how DFHDL simplifies and speeds up the logic design processes and our goals to do the same for verification. Expect a straightforward discussion on how each layer of DFHDL works, why it matters, and what it means for the future of hardware design. We’ll share real-life examples and insights that show DFHDL in action. Whether you’re deep into hardware design or just curious about how chips come to life, this talk has something for you. DFHDL is an opensource framework available at https://dfianthdl.github.io/ (WIP)

BYOL (Build Your Own Linter) - UVMLint for IEEE-UVM core code development

Ajeetha Kumari Venkatesan

UVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have wide user base, longer lifetime and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via GitHub. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around "static const" (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display ("cond"); o if (cond) .. else $display ("Else cond as single line"); o case..endcase • Avoid one-liner code in loops: o for, repeat, while, do..while, foreach • Use enadlabels for elements such as endclass, endfunction, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is quite useless for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs, verify their IPs, systems etc. In this talk we show how we approach this cusotm UVMLint development with sample Python code, tests and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase is below: ** Violation count by Rule-IDs ** DBG_CL_MISSING_ENDLABEL : 286 DBG_METHOD_MISSING_ENDLABEL : 1899 DBG_FN_MISSING_ENDLABEL : 752 DBG_AVOID_ONE_LINER_IF : 73 DBG_AVOID_ONE_LINER_ELSE : 88 RACE_NO_STATIC_CONST : 8 REUSE_NON_VIRTUAL_METHOD : 1407 --- UVMLint Concise Report --- Total number of rules violated: 7

Contact

Please feel free to reach out to the event organizers via orconf@fossi-foundation.org at any point. Or send a message on the Matrix channel: #orconf2024:fossi-foundation.org.