The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of May 4th and 5th in Portland, Oregon, USA.
Latch-Up will be a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf.
Latch-Up is free to attend - however please register so that we can plan better! We expect all participants of FOSSi events to follow the FOSSi Foundation code of conduct.
We encourage anybody involved in the open source semiconductor engineering space to come along and give share your work or experience. Presentations slots as short as 3 minute lightning-talks up to 30 minute talks with Q and A are available.
So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.
Latch-Up is free to attend, but we aim to provide catering and the like during the event. Latch-Up is also a great way to get your company or brand in front of lots of engineers and hackers on the day, and thousands more through recordings of the event. So please get in touch if you'd like to explore sponsorship opportunities.
Latch-Up is organized by volunteers on behalf of the FOSSi Foundation. We are currently looking for more people to help out with arrangements and putting on the event, so please do email us if you would like to voltuneer for during the event with setup, AV, or even just local knowledge so we can plan the weekend better.
You can also support us with small donations via Paypal:
Technically speaking, latch-up is a short circuit, an inadvertent path of low-impedance. We have co-opted this word to represent what we’d like to encourage among members of the community: paths of communication leading to collaboration, inadvertent or not.
Latch-Up 2019 in Portland opens a new chapter for the FOSSi Foundation, with it being the first event in the spirit of ORConf held in North America. Latch-Up is a community-focused conference for open source semiconductor, digital design and embedded systems professionals and enthusiasts. Expect presentations on a wide range of topics; open source IP blocks and SoCs, open source simulators, compilers, synthesis and physical implementation tools for both FPGA and ASIC.
Latch-Up aims to bring together the North American open source digital design community for an event in the mould of ORConf - the FOSSi Foundation’s annual European community conference. Like ORConf, Latch-Up will be will be free to attend and consist of a relaxed format of presentations and discussions throughout a weekend, with plenty of time for networking. A dinner on the Saturday evening will be arranged and all attendees are invited to attend.
These events go to the FOSSi Foundation's goal of lowering barriers of entry to the digital design field, whilst encouraging the open source development model and promoting open collaboration.
We recognise the keen interest in this area in the Americas and this year are putting effort into organizing an event which will encourage wider awareness amongst enthusiasts of the projects that we’ve been hearing about at ORConf since 2012.
The current status of the event is that we are finalizing venue details, which will be close to central Portland. We will update the page and make details known via social media as they emerge.
Despite being sold in the millions, video games based on discrete game ICs have had minimal emulation developed. This is primarily due to the circuitry being a literal "black box" as only the manufacturer possessed the designs. In addition, much of the documentation surrounding these games has disappeared over the years.
Cole has been developing a process to re-implement these stubborn circuits in modern FPGAs as well as software. It involves extracting a transistor-level netlist from high-resolution photographs of the exposed silicon die. Reverse-engineering and slow simulation is achieved using tools pioneered by the visual6502 project. This is followed by reverse-EDA performed by custom tools being developed. The transistor-level design is automatically converted into a more abstract RTL circuit description.
Verilog obtained from the above process will be ported to the tinyFPGA board, the MiSTer hardware emulation project, and the MAME software emulator. The intermediate files will be open-source in the spirit of the target projects.
Cole has only recently joined hardware design circles as a result of his reverse-engineering project, which began over two years ago. He looks forward to potential work on RISC-V and ASIC design in the future.
Open Source VHDL Verification Methodology (OSVVM) is an ASIC level VHDL verification methodology that is simple enough to use even on small FPGA projects. OSVVM offers the same capabilities as other verification languages such as SystemVerilog and UVM.
This presentation provides an overview of OSVVM's capabilities, including:
OSVVM is implemented as a library of free, open-source packages. It uses these packages to create features that rival language based implementations in both conciseness, simplicity, and capability.
In exciting news, The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study, which is sponsored by one of the EDA vendors revealed that OSVVM is the number 1 VHDL FPGA verification library.
Looking to improve your VHDL FPGA verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them."
Jim Lewis has over 30+ years of design, teaching, and problem solving experience and is well known within the VHDL community. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is an expert VHDL trainer for SynthWorks Design Inc. In his design practice, he has created designs for print servers, IMA E1/T1 networking, fighter jets, video phones, and space craft.
LGraph is compiler infrastructure to support hardware languages. The goal is to become the LLVM of hardware. LGraph is a graph optimized for live synthesis and simulation (Live Synthesizes Graph or LGraph for short). By live, we mean that small changes in the design should have results in few seconds. The goal is that any code change can have its synthesis and simulation setup ready under 30 seconds with a goal of under 4 seconds in most cases.
Jose is the lead designer coordinating several students at UCSC on LGraph
SYZYGY is an open standard for high performance peripheral connectivity. All current and past generations of FPGAs differentiate standard I/O pins and transceiver-capable I/O pins at the package level. Therefore, there is no cross-compatibility advantage to using the same connector for both peripheral types. There are several advantages, however, including: lower standard connector cost, lower cable cost for standard peripherals and better pin count utilization for both types.
Tom McLeod is a design engineer at Opal Kelly Inc., the publishers of the SYZYGY specification. He was a member of the group that wrote the SYZYGY specification and has participated in the design of a number of products implementing the specification.
In many ways, HDL developers have been many years behind their counterparts in the software world. One such area is core management. Where the software developers simply specify which libraries they depend on, HDL developers rely on copying around source code. Where software developers can select their build tool with a flick of a switch, HDL developers use tool-specific project files powered by custom makefiles.
FuseSoC rectifies this by bringing a modern package manager and a uniform build system to HDL developers, making it easy to reuse existing code, change tools and move projects between FPGAs from different vendors. Having been around for seven years there are now hundreds of FuseSoC-compatible cores and 14 different simulation, synthesis and lint tools supported. This presentation will give an overview of where FuseSoC can help spending less time on the cores, and more time on the core business
Olof is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations.
Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and ipyxact, the IP-XACT Python library. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.
This presentation will cover Morse Micro's adaptation of the Berkeley/SiFive Rocket chip generator in developing single-chip 802.11ah solutions. We will discuss the pros and cons of Chisel, Rocket's architecture, and aspects of our work in taking the Rocket project and implementing multiple deeply-embedded-class micro-controllers.
Julius has a decade of open source hardware experience through his involvement with the OpenRISC project and later the FOSSi Foundation. Aside from evangelizing for open source digital design, he works as a digital design engineer on mixed signal wireless chips.
Taking a description of components and the connections between them and converting it into a reasonable looking image is a surprisingly complicated problem. Digital netlist visualization is useful for pedagogy, documentation, and debugging and is commonly integrated into proprietary FPGA toolchains such as Vivado or Quartus. Netlistsvg is a simple tool that takes yosys netlists in JSON format, and attempts to create an easily understandable image in SVG format.
Neil is a Software Engineer at National Instruments on the CompactRIO team. Netlistsvg has been a personal project of his for a few years.
OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technology.
Matthew Guthaus is a Professor at the University of California Santa Cruz in the Computer Science and Engineering department. His research interests are in low-power computing and computer-aided design. This includes new circuits, architectures, and software to address integration in modern design flows.
FPGA (and ASIC) hardware development requires EDA tools for simulation, debugging, embedded software development, synthesis, and a host of other tasks. Installing, configuring, and managing this software -- whether or not it's open source software -- can be time consuming, and makes it more difficult to get started developing open-source silicon.
EDAPack provides a framework to make these tasks easy. This talk will explore the motivation behind EDAPack, and how EDAPack simplifies EDA tool management.
Matthew Ballance is a Product Engineer at Mentor, A Siemens Business working with Portable Stimulus. Over the past 20 years in the EDA industry, he has worked in product development, marketing, and management roles in the areas of hardware/software co-verification, transaction-level modeling, IP encapsulation and reuse, and Portable Test and Stimulus. Nights and weekends, Matthew works on open-source hardware and software projects. Matthew launched EDAPack in frustration when faced with the task of configuring yet another machine with his favorite EDA tools.