Step with us into the Quantum-Nano Fabrication and Characterization Facility, aka Nanofab at the University of Waterloo! See and learn about the advanced equipment that make chip designs actually work in the real world.

Separate registration required, watch your email inbox for details shortly before the event.

Welcome to Latch-Up! All you need to know to have a successful conference.

As python-based build systems such as FuseSoC and SiliconCompiler gain adoption across the industry, projects are becoming increasingly tied one ecosystem or another. This lock-in limits teams' ability to use hardware IP and leverage tool flows developed in other ecosystems.

This presentation introduces a new approach for interoperability between build systems, along with a supporting library that enables compatibility between FuseSoC's cores and SiliconCompiler's libraries. By lowering switching costs, we aim to increase IP reuse, reduce engineering duplication, and allow teams to choose the right tool for each stage of the design process

The award-winning FuseSoC is the world's most widely used package manager for chip design and powers everything from small hobbyist FPGA projects to multi-billion transistor ASIC tapeouts on leading-edge nodes.

Despite the benefits, there is often a fear associated with moving to a new system. As FuseSoC developers, we often hear "It won't work for our code base" or "we have some special requirements". Well, my friends. This presentation is for you. It is also for all of you who are already using FuseSoC but perhaps hasn't picked up how to unlock its full potential. We will look at some of the convenient features that sometimes are missed, adaptations that are often used when FuseSoC is introduced into an existing code base as well as sorting out some common misconceptions that we have come across when working closely with FuseSoC users with large code bases.

Erbium is the first tapeout of AIFoundry's open-source manycore ASIC platform for parallel computing acceleration. This 8C16T RISC-V SOC with Vector and Tensor extensions is targeted towards the EdgeAI application space. In this talk we will cover

1. The ISA, Memory and SOC design.
2. The design process.
3. Verification Flow.
4. The current state of opensourcing the design.

Attendees will learn about the opensource components that can be reused in their design and contributing to the growing community of Silicon and Software developers at AIFoundry.

Step with us into the Quantum-Nano Fabrication and Characterization Facility, aka Nanofab at the University of Waterloo! See and learn about the advanced equipment that make chip designs actually work in the real world.

Separate registration required, watch your email inbox for details shortly before the event.

CHIPS Alliance hosts open source tools and IP blocks for ASIC development, and has a vision of aligning open source efforts towards building a tool suite for faster and more collaborative design and testing of silicon.

This talk will outline the activities and objectives of the recently restructured SV Tools project, concerned with SV development, testing and productivity with CHIPS-hosted tools like Verible, RISC-V DV or SV-tests and their integration with the broader open source tooling ecosystem, as well as new developments in the VeeR family of RISC-V cores, including the Guineveer SoC based on the Topwrap SoC generator.

Open-source electronic design automation (EDA) tools and accessible fabrication platforms are transforming how integrated circuits are designed, enabling broader participation in silicon development beyond traditional industrial environments. The Chipathon is a global open-source IC design challenge organized under the IEEE Solid-State Circuits Society (SSCS) PICO (Platform for IC Design Outreach) initiative. The program aims to democratize chip design by providing students, educators, and researchers with a structured pathway to design, verify, and potentially fabricate integrated circuits using open-source tools and publicly accessible process design kits.

The Chipathon combines a multi-month design competition with a culminating workshop where participants present their designs, methodologies, and lessons learned. Teams develop innovative circuit blocks and systems across multiple tracks, including digital systems, analog and mixed-signal circuits, AI-assisted design flows, and reusable open-source building blocks. Emphasis is placed on reproducibility, open collaboration, and transparent evaluation through shared design artifacts, verification methodologies, and benchmark metrics.

By integrating education, open-source infrastructure, and real silicon opportunities, Chipathon lowers barriers to entry for integrated circuit design and fosters a new generation of hardware innovators. The program also serves as a testbed for emerging design methodologies—including AI-assisted EDA workflows—and promotes the development of reusable circuit intellectual property for the open-source hardware ecosystem. Through its global participation and collaborative spirit, Chipathon advances the SSCS mission of expanding access to chip design education and accelerating innovation in the semiconductor community.

The TinyTapeout FabricFox breakout brings an FPGA onto a board pin-compatible with the TinyTapeout demoboard, enabling designers to validate their synthesized implementation on real hardware before committing to silicon.

This talk covers how the breakout slots into the open-source ASIC design flow: local or github-action based hardening, a unified microPython SDK for project selection and hardware control, and custom Python or microcotb for hardware-in-the-loop testbenches that mirror simulation. The same demoboard hosts both FPGA prototype and final ASIC--making physical validation a first-class step in the loop, not an afterthought.

The result is a tight, open-source loop from simulation → FPGA → silicon that dramatically accelerates iteration while keeping every step reproducible and accessible to the FOSSi community. Come see how this tiny board closes the gap between prototype and tapeout.

How to form an open source community that's not just publishing code, but also sustains itself? Frans will look at two examples: the Surfer waveform viewer, and cocotb.

This talk outlines the University of Toronto ASIC Team's initiative to democratize silicon engineering by leveraging the Free and Open Source Silicon (FOSSi) ecosystem.

By adopting open-source tools the team enables undergraduates to experience the complete design cycle, resulting in tangible tapeouts through services like TinyTapeout. The presentation will detail the team's extracurricular impact—including the university's first IC Design Hackathon—and its strategic partnership with the ECE faculty to rewrite and modernize core course laboratories. This integration of open-source methodologies into both student competitions and formal lab curricula demonstrates a scalable model for making engineering education more practical and industry-relevant.

Hudson River Trading continues to push the bounds of what is possible with Verilator. This talk will explore several improvements and fixes we've made to the tool. We'll discuss the rationale for these changes and how they relate to our build and test ecosystem.

Building on our ORConf 2025 verification in Verilator (https://fossi-foundation.org/orconf/2025#advancing-design-verification-with-verilator) presentation, in this talk we'll dive into further progress Antmicro and others have made with regard to Verilator's verification capabilities. We will cover topics like improvements to UVM compatibility, developments in assertion support, an overhaul of force/release statements, and the next big step for Verilator: four-state logic. We will also touch on tools that helped us get here, such as sv-bugpoint or CHIPS Alliance's sv-tests.

The design of advanced Analog chips‚ especially in photonics, quantum, MEMS, and RF, faces critical challenges due to rigid, outdated EDA tools. Many teams resort to custom Python, C, or MATLAB solutions, which offer flexibility but lack scalability. To bridge this gap, we created GDSFactory, an open-source, python-based Analog Electronic Design Automation software that has been downloaded over 2 million times and adopted by companies, universities, and research organizations worldwide.

Vaporview is a waveform viewer extension for VS Code. It was first presented on at Latch-Up last year, and has since grown in popularity. In this year's presentation, I will give a brief update on new features, and then discuss the project architecture and the design process I used to create Vaporview.

Mr. Scrub is an open-source, internal scrubber for AMD’s UltraScale FPGAs. We document the algorithms used for SECDED of the device’s configuration frames. We also describe validation of the scrubber using fault injection.

Modern FPGAs can swap out a hardware module at runtime while the rest of the chip keeps running, this is partial reconfiguration. But when you try to verify that behavior in simulation, you hit a wall: Verilator and other simulators compile the entire design into a single binary at elaboration time, and cocotb's runtime assumes the module hierarchy never changes. Today, the only way to test a different module configuration is to recompile and restart the simulation from scratch, making it impossible to verify sequences of runtime swaps without deploying to physical hardware.

We present a multi-process simulation architecture that lets cocotb test arbitrary module swaps mid-simulation without modifying cocotb or Verilator. The key idea is to run each swappable module as an independent simulator process. In the main simulation, the module's slot is filled by an adapter which cocotb sees as a normal module, but under the hood, can shuttle signal values to and from the appropriate reconfigurable module simulator processes over shared memory. A lock-free barrier synchronizes all processes at every clock cycle. Swapping a module is just an OS-level process replacement: kill the old one, start the new one, resume the barrier. cocotb's VPI state, Python objects, and test flow are completely undisturbed.

Designing new FPGAs, or embedding FPGA logic into a larger SoC, has historically been difficult because expensive full custom design was needed to create the physical FPGA and CAD tools did not exist for the new architecture. Open-source tools like Verilog to Routing (VTR), OpenFPGA, and Zero ASIC's Logik flow are changing this, dramatically lowering the barrier to building and using custom FPGA architectures. This talk gives a brief tour of these open-source tools, then highlights recent work by the author: a fast, standalone visualizer for VTR architecture descriptions that makes debugging and designing custom FPGA models easier.

Working on open-source RISC-V cores is undoubtedly cool, but the real thrill came from taking the leap and fabricating an actual silicon chip. To turn this ambitious vision into reality, we partnered with the University of Saskatchewan and several other dedicated collaborators. After the successful production of our initial chip, our friends at USask proposed a brilliant next step: leveraging their research to radiation-harden the design. The goal? To launch it into space! So, we did exactly that—we hardened the core and spun a new, space-ready chip. If you're eager to get your hands on the source code for the MCU (which is based on the OpenHW Foundation's CV32E40P), you'll find it below. Feel free to fork the repository or join us as we begin work on the next-generation version.

After the shutdown of Efabless in February 2025, Cadence ran their first shuttle on Sky130 with a generous invitation to the open source silicon community. I submitted five chips, to recover some of the silicon lost in the Efabless shutdown. Subsequently, I ported "openframe" designs to GF180MCU on Wafer.Space and SG13CMOS5L on IHP. I will present on challenges of the tapeouts, resolutions, and upcoming work.

Now that it's possible to tape-out an analog open source design, you might find yourself in the predicament of having to layout a design manually - full custom. This talk will provide a brief overview of the process, as well as best practices for designing good, reliable layout to get you started on your full custom journey!

Substrate is an open-source, statically typed framework for creating highly configurable schematic and layout generators using the Rust programming language. Substrate provides multiple levels of abstraction, allowing designers to navigate the tradeoff between fine-grained control over a design and increased automation. We also describe algorithms for programmatically creating and modifying circuit layouts, including two methods for automatically adjusting the aspect ratio of a layout. We use Substrate to design generators for a StrongARM comparator and a programmable resistor bank in Skywater 130nm and Intel 16nm, demonstrating 90 degree rotation, array folding, and the ability to change the aspect ratio by a factor of over 10 in both processes. These generators highlight Substrate's ability to facilitate design reuse, process portability, and performance and area optimization.

Analog integrated circuit layout remains intensely manual, requiring weeks of expert effort. We present CLARA's multi-objective reward function that decomposes layout quality into interpretable components: symmetry, compactness, connectivity, and device grouping. Unlike sparse terminal rewards, our graduated penalty system provides dense feedback that scales proportionally to constraint violations. Validation across three SKY130 circuits demonstrates convergence from severely constraint-violating states to fully feasible layouts, with device grouping driving optimization while revealing fundamental trade-offs between matching and geometric efficiency.

Open-source silicon reaching real products is the moment the ecosystem matures from a research tool into infrastructure — the same transition Linux made when it started running production servers. Products impose the constraints that drive quality: a battery life target forces low- power verification, a temperature spec forces worst-case timing closure, a BOM cost goal forces die area discipline. These are the rigors that transform open IP blocks from tapeout artifacts into components the industry can trust, and that open custom silicon to the thousands of product companies that have never had access to it. The open-source stack is ready for this — open PDKs, automated RTL-to-GDSII, a proven SoC harness, and shared-wafer shuttles that make silicon accessible. The tools are no longer the barrier. The next step is ours to take.​​​​​​​​​​​​​​​​

This talk presents the current status of the IHP openPDKs and the open-silicon MPW program, highlighting the significant progress made over the past four years toward enabling productive chip design with open-source tools. A particular focus is placed on new analoge design capabilities and enhanced RF design features.

In addition, we introduce the open MPW and open-silicon concepts, which provide silicon access for validation and evaluation of submitted open-source designs. Finally, we outline upcoming projects in tool and PDK development, emphasizing future directions for both design tools and technology enablement.

Coding agents and agentic software development are changing EDA development, most visibly and straightforwardly in the realm of permissive open source. Recent advances span agentic flow tuning and local optimization; repo-scale, closed-loop autonomous coding pipelines; and bespoke EDA tools and flows to achieve design-specific optimization goals. At the same time, models, multi-agent architectures, and value propositions are also rapidly evolving. Open-source EDA thus faces a host of new challenges – validation and evaluation; balancing of humans and agents; IP and creators’ rights; project and ecosystem governance; and many more. This talk will give some thoughts on the above – recent progress, emerging challenges, and new opportunities – from the perspective of the OpenROAD project.

We present a two-year effort at UC Santa Cruz to build an open source 1.58-bit LLM accelerator targeting Ridger Chu's MatMul-Free LLM family (370M, 1.3B, 2.7B parameters). The design compiles a full transformer inference pass to an instruction stream, executed on hardware functional units for ternary matrix multiply, RMS norm, and rowwise arithmetic. A software emulator validates numerical correctness against the official model before synthesis. The design scales from ~30 tokens/second on a low-cost Artix-7 to over 1000 tokens/second on an Alveo U250 Ultrascale+, with a live demo on a NiteFury II PCIe board. Because every weight is in {-1, 0, 1}, multiply-accumulate reduces to addition and weight storage shrinks dramatically, making these models uniquely suited for FPGA acceleration. We also share valuable lessons from building this entirely with open source tooling: why sv2v proved more consistent than slang or yosys-sv as a SystemVerilog frontend, how Xilinx's open-sourced unisim libraries enabled us to track down and work around simulation bugs, and the Verilator issues we filed along the way.

FSMs drive the control plane of hardware: sequences, protocols, arbitration, and recovery logic. Despite language evolution, the way FSMs are written often has not changed. Many "high level" HDLs still express sequencing using the same legacy structure: explicit state variables, explicit transitions, and growing scaffolding as designs evolve. This talk shows a few concrete examples where modern syntax and tooling still lead back to the classic FSM pattern, and why that pattern becomes brittle at scale. Then we focus on the hidden gem: Bluespec. With guarded atomic actions and sequencing as first-class concepts, Bluespec changes the shape of FSM code, making control intent clearer and large stateful behavior more maintainable.

Introducing a new addition to your quiver of PeakRDL tools: PeakRDL-PyRAL Register abstraction layers provide a mechanism to manipulate your device's configuration and status registers (CSR) by name rather than by cryptic addresses and bit-slicing. In Python, this abstraction is often provided using auto-generated Python code that is parsed and imported at runtime. For larger designs, this can become a significant burden due to slow load times and large memory overheads. Learn how PeakRDL PyRAL avoids this issue and provides an easy to use abstraction layer that can scale to enormous SoC-level designs that contain thousands of memory-mapped registers. PeakRDL-PyRAL is flexible enough for anything from embedded applications, hardware test instrumentation, to your next cocotb testbench.

Silicon engineering demands multiple model types — architecture, behavioral, RTL, and test. These typically all use different languages, limiting reuse and forcing teams to maintain disconnected -- possibly inconsistent -- descriptions of the same design.

Zuspec provides a unified Python-based hardware modeling language that covers design and verification. A model written with Zuspec can be can be evaluated statistically, simulated at native-compiled speed, and refined to synthesizable RTL.

Hardware design with Zuspec is progressive: add detail to a shared model instead of starting over at each abstraction. This makes cross-functional collaboration natural, while new synthesizable constructs and design patterns open up a richer micro-architecture design space.

Spade is a modern hardware description language that brings a powerful type system, abstractions for hardware constructs like pipelines and memories, and user friendly tooling to the hardware space. In September 2025, the language turned 5 years old, and this presentation will show off the current status of the project, the new development since the last LatchUp presentation two years ago, and perhaps some new things coming in the future.

We’ve developed an event based framework in modern C++ to do hardware verification. This framework, which is implemented in a header-only library, is useful for tracking activity in a DUT. It implements a normal producer and consumer callback scheme, as well as some more unique and novel features such as event history, delayed callbacks, event filtering mechanisms, and clock configurability that make it particularly suited for hardware verification.

Rivet is a hardware design flow manager built in the Rust programming language. It implements TCL templating with plugins for foundry PDKs (including SKY130) and industry-standard tools, e.g., Genus, Innovus, and Pegasus from Cadence. Rivet features shared checkpointing, pinning dependencies, and support for hierarchical designs.

Open-source RISC-V cores such as VexRiscv offer flexible architectures for embedded FPGA and ASIC implementations, but instruction cache configurations significantly influence performance, area, and power trade-offs. This work presents a quantitative analysis of instruction cache optimization within the VexRiscv core, evaluating performance impacts across multiple cache configurations in resource-constrained environments. Through synthesis and benchmarking on FPGA and ASIC-targeted workflows, we analyze utilization, and efficiency metrics to identify optimal design trade-offs. Results demonstrate measurable improvements in performance-per-resource metrics. These findings provide practical guidance for designers leveraging VexRiscv in customized RISC-V implementations.

Following NIST’s selection of the Ascon family as the lightweight cryptography standard (SP 800-232), this work presents a hardware accelerator targeting its core primitives. Ascon provides efficient AEAD and hashing through a 320-bit permutation design, optimized for resource-constrained devices such as IoT and embedded systems. Our implementation focuses on Ascon-128 and Ascon-Hash, offloading compute-intensive operations to dedicated hardware. This approach significantly improves throughput and energy efficiency, enabling practical, real-time security for low-power FPGA and ASIC deployments.