CHERI (Capability Enhanced RISC Instructions) is an extension to instruction set architectures that provides new primitives which can be used to enforce least privileged access to memory. This extension greatly reduces the risk of and reach of most security vulnerabilities. CHERIoT is CHERI designed for resource-constrained, embedded systems. Microsoft extended the lowRISC maintained Ibex Core with CHERIoT and created an RTOS that fully utilises CHERIoT.

The Sunburst Project is a, UKRI/DSbD funded, lowRISC project with the goal of helping CHERIoT technologies traverse the gap from academia to industry. After one and a half years, phases 1 & 2 of the project are all wrapped up having surpassed its original objectives. The two most consequential FOSS outputs are the Sonata™ development platform and the recently announced Sunburst chip repository. The Sonata™ platform is the combination of a full developer tool-chain and an FPGA evaluation board for experimenting with CHERIoT. Sunburst chip leverages open source hardware IP blocks from the open source OpenTitan Project that have received industry level verification into an open SoC design with a full design verification environment and a formally verified CHERIoT enabled RISC-V core. SCI Semiconductor is using the Sunburst chip as the foundation of their new ICENI microcontroller which will have its first tape-out later this year.

The Sunburst / CHERIoT Hardware Enablement Project has been funded by DSbD / UKRI - Grant Number: 107540

A simple methodology for modelling digital signal processing was introduced at ORConf 2024. This has been greatly extended and now includes performance measurement (signal and band limited noise level, IMD, THD etc), fixed point arithmetic modeling, and frequency response determination - both directly at the transfer function level, and extracted from time domain simulation.

Accelerating agile hardware design requires aggressive reuse of libraries and methodologies. While libraries like Basejump STL, PULP Platform Common Cells and Chipyard excel at providing portability layers and low-level components (e.g. FIFOs, memories), and SoCs rely on hardened IP blocks for larger components (e.g. off-chip PHYs, processor cores), there remains a gap in reuseable blocks between these levels.

bsg_pearls bridges this gap by offering a library of mid-level synthesizable components - such as SDR links, DDR links, clock generators, LPDDR controllers - that can be seamlessly integrated into soft designs. Each submodule contains SystemVerilog design files, a synthesizable testbench, vendor-agnostic TCL constraints and technology-agnostic placement guidelines. By construction, pearls are highly runtime configurable and (mostly) decoupled from external timing paths, enabling early hardening in the design process. This drastically reduces full-chip iteration time while maintaining flexibility in immature RTL.

In this talk, I will present the philosophy and architecture of bsg_pearls; explore their use in real-world chip designs; discuss integration plans with open-source tooling; and invite feedback from the open-source hardware community to drive adoption!

There are many existing libraries, both commercially licensed and free-and-open-source, for describing digital fixed-point arithmetic in hardware, but they all share some undesirable features.

A fixed point number is usually described by fixed information including the width of the binary number in bits, and their significance in a fixed point environment. For example, a 16 bit hardware value could represent numbers in the range 0..65536 notated as unsigned(16,0), or between -32768..32767 notated as signed(16,0), or as a number in the range -1..255/256 notated as signed(8,8) or as a number between -1..32767/32768 notated as signed(1,15), or many other options. A key question is what is the result type when two 16 bit numbers in the same format are added? - in some cases a 16 bit result is expected (with modulo or overflowing behavior), but in many cases, a wider 17 bit result is wanted and expected.

Normal mathematical arithmetic is associative, where the ordering of addition is not important, but perhaps surprisingly, most fixed point library types are not. Most existing fixed point libraries will overly widen the result type width when multiple additions are performed. The value of using a fixed point library is severely diminished whenever the design engineer needs to override the widths that were determined automatically.

The parameterization used here is very simple as it treats signed and unsigned representations equivalently. It neatly distinguishes between the cases where modulo overflow should be expected versus non-overflowing arithmetic with word length growth. It can also distinguish between variables which require storage and constant fixed-point values which do not. This is all achieved in a simple, mathematically pure manner.

Floating point types are not included, but the formulation has been used for describing hardware implementing floating point arithmetic and floating point function approximations.

This formulation is ideally suited for incorporation into future hardware description languages.

An update on another year of Chisel development.

Hardcaml is an embedded DSL in OCaml designed for high-performance FPGA designs. This talk will go over the design of Hardcaml, providing general principles for designing new embedded DSLs for hardware design, and showcase how Hardcaml enables both high-level abstraction and low-level optimizations.

Nearly every IP core, peripheral, and SoC requires a software register interface. Along with that you need software headers, test APIs, and good documentation. Wouldn't it be great to automate all of this using a single source of truth?

Fortunately a ready-to-use toolchain already exists! PeakRDL is a free and open register map automation toolchain that is designed around SystemRDL - an industry-standard CSR specification language.

In this talk, discover how these silicon-proven tools can be used to generate synthesizable RTL, impressive documentation, software abstraction layers, and be extended using an intuitive Python API. This presentation will also review the latest updates to the PeakRDL and SystemRDL compiler tools, as well as a preview of what is planned for the future.

Join the growing community of people building extensions for PeakRDL, and fulfilling the vision that high-quality CSR automation ought to be free to everyone.

Learn more at: https://github.com/SystemRDL

Europe is stepping up in Open Source Chip Design by funding various parts of the ecosystem. In particular, currently Open Source EDA tools are in the focus, attracting 40+ million Euro in funding.

This presentation gives a brief overview of how FOSSi Foundation played an integral role in this effort and how the community will benefit from, and which challenges are ahead.

The “One Student One Chip” (OSOC) initiative was launched by the University of Chinese Academy of Sciences in 2019. The initiative guides students through designing a RISC-V processor chip from scratch, including tape-out, developing a simple operating system, running it on the chip, running the real game Legend of Sword and Fairy, and completing the physical design process using open-source EDA tools. This enables students to understand the entire processor chip design process. As of February 2025, the total number of OSOC enrollments has exceeded 10,000. This report introduces the implementation of the “One Student One Chip” initiative and the outcomes of open-source chip talent cultivation.

In this talk, we will introduce the open silicon education course by using open-source EDA toolchain (Yosys, cocotb, iEDA etc.) on IHP130 open PDK powered by cloud platform, with the primary objective to fill the gap between academic and industry. This course is currently under development and will be released in 2025Q2 with rich materials (lecture notes, slides, hands-on labs) and infrastructure support (RTL2GDS flow, LMS, cloud platform, etc.). Additionally, we will show a full practice on designing an education-oriented test chip (called “retroSoC”) to verify our new end-to-end workflow (Yosys+iEDA+IHP130) with cloud platform. Finally, we will further share more technical details on our EDA cloud platform and explore the performance boundaries by reimplementing some complicated SoCs on cloud platform. We hope this process can help us figure out performance bottleneck and promote the development of open EDA toolchain to make it suitable for various industry application scenario in the future.

Creating adequate test content to verify hardware designs across the IP to SoC process presents a a continual challenge for verification engineers. It certainly doesn't help that the unique goals, current verification languages, and restrictions of each verification platform make reuse of test content challenging and effort intensive.

Accellera Portable Stimulus Specification (PSS) language is a test-content modeling language that enables test content reuse from block IP to SoC and across simulation, hardware emulation, and silicon platforms. PSS provides zero-cost abstraction language features that model common verification scenarios, such as concurrency and resource contention, enabling compilation tools to create efficient platform-appropriate implementations.

This talk will provide an example-driven introduction to the PSS language, and provide resources and details of available open source tools that support learning about and using PSS.

The FOSSi Foundation takes ensures that the Free and Open Source Silicon community has places to come together, share experiences, and don't worry about administrative tasks too much. In this talk, we'll look at the initiatives the FOSSi FOundation is involved in, and what changed since you might last have heard of it!

While open source waveform viewers had existed, I wanted something that provided the integrated development experience that big vendor tools had. This is the story of developing a waveform viewer in VScode; why I built it, and where I intend to take the project.

BenchBot is an open-source Python tool that automates the creation of OSVVM-compliant testbenches for VHDL designs. It uses YAML configurations to define key parameters and generates a structured test environment. The generated testbenches include essential components such as clock and reset generators, stimulus handlers, and watchdog mechanisms. BenchBot also supports modular and distributed test development within the OSVVM framework. This version builds on the previous generation developed in 2024. It introduces new features such as an enhanced functional coverage model for bit vectors and expanded simulator support. These improvements extend the capabilities of the generated VHDL testbenches, making them more versatile and comprehensive. Additionally, the Python codebase has been completely refactored. The new implementation follows standard object-oriented programming (OOP) principles, improving code readability and maintainability. The structured design makes it easier to extend and adapt the tool for future enhancements.

In this talk, we will first discuss the complete refactoring of BenchBot’s Python codebase. The new implementation follows standard object-oriented programming (OOP) principles, making the code more modular, readable, and maintainable. This structured design simplifies future enhancements and allows easier customization. Next, we will highlight the new features added to the generated VHDL testbenches. These include an enhanced functional coverage model for bit vectors, improving verification completeness. Additionally, we will discuss how BenchBot now supports more simulators, including NVC, expanding its usability across different verification environments.

Yuvan Pradeep, High school student, American High School, Fremont, CA (yuvvvan02@gmail.com) Adruth Vasudevan Srinivasan, Secondary School Student, The Forest Academy, Ilford, London, UK (adruthv@gmail.com) Ajeetha Kumari Venkatesan, AsFigo (ajeethak@asfigo.com)

Almost all real-world logic designs (FPGA and ASIC) require use of multiple clock domains. Techniques have been established to move information between clock domains (clock domain crossing, shortened to CDC). It is easy, however, to lose track of where CDC happens in a large HDL code base, especially one that evolves as a collaborative effort. Our cdc_snitch tool leverages yosys' logic synthesis and transformation capabilities to analyze a design and find anti-patterns of CDC design. This visibility has helped us improve our code quality, and is now a part of our continuous integration (CI) workflow.

During the chip development process, engineers need to target different technologies to support different deployment platforms, such as simulation, ASIC and FPGA technologies. Conventionally, they do this by splitting parts of the HDL (hardware description language) code into separate blocks for each technology (e.g., memories), implementing the same high-level behavior for each block but specialized for a given technology. This approach leads to a brittle code base, with multiple but subtly different technology-specific blocks of code describing the same semantic behavior, increasing the burden on verification, agility, and extensibility. The insight in this work is incorporating an abstract memory representation into the HDL which is "write once, map anywhere", meaning the memory representation has a rich enough semantics to target all of the relevant technologies using a single generic interface.

This DSL, called a memory design language, enables automated technology mapping for memories. Further, for designs coming from other HDLs which are already mapped to a specific technology, I also present a hardware decompilation-based memory inference technique which lifts memories from a gate-level design to an abstract memory block, enabling automated technology re-targeting, a holy grail for digital designers. The key mechanism of the approach is a unified set of algebraic rewrite rules based around memory block semantics. The technique leverages equality saturation to explore a large space of designs according to technology constraints, with the ability to elaborate "forwards" and "backwards". The memory design language targets five backends for three different technology platforms (simulation, ASIC, and FPGA). Further, decompilation-based memory inference outperforms the state of the art, demonstrating higher accuracy and enabling automated re-targeting.

svck is an open-source, minimalist linter designed to svck is an open-source, minimalist linter designed to enforce style and consistency rules for SystemVerilog code. It provides a Build Your Own Linter (BYOL) framework, allowing users to define custom linting rules while leveraging built-in checks for naming conventions, encapsulation, line spacing, and more. svck integrates seamlessly into CI/CD pipelines, ensuring maintainable and high-quality HDL code.

Unlike ad-hoc regex or Perl-based scripts, svck is a professional-grade linter built on Google’s open-source Verible parser. This foundation makes it far more scalable, robust, and accurate, ensuring reliable rule enforcement across large and complex codebases. Its modular architecture allows easy customization, enabling users to define new lint rules tailored to their verification and design needs.

This talk will explore svck’s architecture, its use of Verible for syntax parsing, and the flexibility offered by BYOL. We will demonstrate its application in real-world verification workflows and discuss community contributions that continue to shape its development.enforce style and consistency rules for SystemVerilog code.

GDSFactory is a powerful Python library for designing a wide range of complex systems, including photonic circuits, analog devices, quantum components, MEMs, 3D printed objects, and PCBs. With GDSFactory, you can create and refine your designs using Python or YAML, perform rigorous verification through Design Rule Checking (DRC), Layout Versus Schematic (LVS) checks, and simulations. Additionally, it facilitates automated lab testing to ensure that your fabricated devices meet precise specifications, streamlining the entire design-to-fabrication workflow.

Static timing analysis (STA) is critical for ensuring that a chip will behave as expected post-tapeout. In this talk, I will give a brief intro to the basic concepts in STA, and will provide examples in OpenSTA, the leading open-source tool in VLSI timing/power analysis. I will talk about the implementation of Synopsys Design Constraints (SDC) and Liberty Non-Linear Delay Model (NLDM) with examples. I will finally discuss how OpenSTA can be bolted onto other tools as a robust timing engine.

Existing state-of-the-art technology mappers struggle to map designs to complex, programmable FPGA primitives such as DSPs. In this talk, I promote my open-source technology mapper Lakeroad, which is able to more completely utilize programmable primitives via its use of a technique called program synthesis. Lakeroad is readily available as a Yosys plugin, and I am actively looking for test users.

A fast-paced deep-dive into various topics.

fplib is a synthesizable SystemVerilog library for working with fixed-point (FP) numbers. This library abstracts out the error-prone task of working with FP numbers, such as keeping track of the integer and fractional bits (the binary point) when doing add/multiply operations. fplib works by (ab)using SystemVerilog interfaces to encapsulate a normal logic vector as well as the parameters for the number of int/frac bits into a single object which can be passed through modules (in the absence of proper language support like in VHDL)

We are a group of ~10 hobbyists building chips in our garage using FOSS hardware such as the Hacker Fab stepper, Maasi spin coater, and DIY tube furnaces

With the recent collapse of Efabless, Tim 'mithro' Ansell has stepped up to provide a new pathway for manufacturing silicon based on the open source GF180MCU process technology.

In this talk, I will be summarizing the current state of the research/deployment of agentic AI applied to the hardware design and verification space. I will give a brief overview of how FOSS projects enable this work and potential contributions we plan to make in the future to evaluate efficacy of these tools in order to enhance certain hardware workflows.

Although the SkyWater 130 nm PDK is an invaluable VLSI teaching resource, no open-source, transistor-level schematics exist—until now. UCSC students are re-creating the entire set of standard-cell in xschem under an open license. These xschem diagrams are already in use in UCSC courses, providing clear transistor-level visuals and deeper insight into how cells are actually implemented. We welcome collaborators to help expand the library! Learn more or contribute at https://github.com/sifferman/sky130_schematics

Packet Badger is an Open Source field-proven digital logic design, implemented on an FPGA, that digs through gigabit Ethernet packets to construct a response.