The “One Student One Chip” (OSOC) initiative was launched by the University of Chinese Academy of Sciences in 2019. The initiative guides students through designing a RISC-V processor chip from scratch, including tape-out, developing a simple operating system, running it on the chip, running the real game Legend of Sword and Fairy, and completing the physical design process using open-source EDA tools. This enables students to understand the entire processor chip design process. As of February 2025, the total number of OSOC enrollments has exceeded 10,000. This report introduces the implementation of the “One Student One Chip” initiative and the outcomes of open-source chip talent cultivation.

A simple methodology for modelling digital signal processing was introduced at ORConf 2024. This has been greatly extended and now includes performance measurement (signal and band limited noise level, IMD, THD etc), fixed point arithmetic modeling, and frequency response determination - both directly at the transfer function level, and extracted from time domain simulation.

GDSFactory is a powerful Python library for designing a wide range of complex systems, including photonic circuits, analog devices, quantum components, MEMs, 3D printed objects, and PCBs. With GDSFactory, you can create and refine your designs using Python or YAML, perform rigorous verification through Design Rule Checking (DRC), Layout Versus Schematic (LVS) checks, and simulations. Additionally, it facilitates automated lab testing to ensure that your fabricated devices meet precise specifications, streamlining the entire design-to-fabrication workflow.

Nearly every IP core, peripheral, and SoC requires a software register interface. Along with that you need software headers, test APIs, and good documentation. Wouldn't it be great to automate all of this using a single source of truth?

Fortunately a ready-to-use toolchain already exists! PeakRDL is a free and open register map automation toolchain that is designed around SystemRDL - an industry-standard CSR specification language.

In this talk, discover how these silicon-proven tools can be used to generate synthesizable RTL, impressive documentation, software abstraction layers, and be extended using an intuitive Python API. This presentation will also review the latest updates to the PeakRDL and SystemRDL compiler tools, as well as a preview of what is planned for the future.

Join the growing community of people building extensions for PeakRDL, and fulfilling the vision that high-quality CSR automation ought to be free to everyone.

Learn more at: https://github.com/SystemRDL

BenchBot is an open-source Python tool that automates the creation of OSVVM-compliant testbenches for VHDL designs. It uses YAML configurations to define key parameters and generates a structured test environment. The generated testbenches include essential components such as clock and reset generators, stimulus handlers, and watchdog mechanisms. BenchBot also supports modular and distributed test development within the OSVVM framework. This version builds on the previous generation developed in 2024. It introduces new features such as an enhanced functional coverage model for bit vectors and expanded simulator support. These improvements extend the capabilities of the generated VHDL testbenches, making them more versatile and comprehensive. Additionally, the Python codebase has been completely refactored. The new implementation follows standard object-oriented programming (OOP) principles, improving code readability and maintainability. The structured design makes it easier to extend and adapt the tool for future enhancements.

In this talk, we will first discuss the complete refactoring of BenchBot’s Python codebase. The new implementation follows standard object-oriented programming (OOP) principles, making the code more modular, readable, and maintainable. This structured design simplifies future enhancements and allows easier customization. Next, we will highlight the new features added to the generated VHDL testbenches. These include an enhanced functional coverage model for bit vectors, improving verification completeness. Additionally, we will discuss how BenchBot now supports more simulators, including NVC, expanding its usability across different verification environments.

Yuvan Pradeep, High school student, American High School, Fremont, CA (yuvvvan02@gmail.com) Adruth Vasudevan Srinivasan, Secondary School Student, The Forest Academy, Ilford, London, UK (adruthv@gmail.com) Ajeetha Kumari Venkatesan, AsFigo (ajeethak@asfigo.com)

During the chip development process, engineers need to target different technologies to support different deployment platforms, such as simulation, ASIC and FPGA technologies. Conventionally, they do this by splitting parts of the HDL (hardware description language) code into separate blocks for each technology (e.g., memories), implementing the same high-level behavior for each block but specialized for a given technology. This approach leads to a brittle code base, with multiple but subtly different technology-specific blocks of code describing the same semantic behavior, increasing the burden on verification, agility, and extensibility. The insight in this work is incorporating an abstract memory representation into the HDL which is "write once, map anywhere", meaning the memory representation has a rich enough semantics to target all of the relevant technologies using a single generic interface.

This DSL, called a memory design language, enables automated technology mapping for memories. Further, for designs coming from other HDLs which are already mapped to a specific technology, I also present a hardware decompilation-based memory inference technique which lifts memories from a gate-level design to an abstract memory block, enabling automated technology re-targeting, a holy grail for digital designers. The key mechanism of the approach is a unified set of algebraic rewrite rules based around memory block semantics. The technique leverages equality saturation to explore a large space of designs according to technology constraints, with the ability to elaborate "forwards" and "backwards". The memory design language targets five backends for three different technology platforms (simulation, ASIC, and FPGA). Further, decompilation-based memory inference outperforms the state of the art, demonstrating higher accuracy and enabling automated re-targeting.

Almost all real-world logic designs (FPGA and ASIC) require use of multiple clock domains. Techniques have been established to move information between clock domains (clock domain crossing, shortened to CDC). It is easy, however, to lose track of where CDC happens in a large HDL code base, especially one that evolves as a collaborative effort. Our cdc_snitch tool leverages yosys' logic synthesis and transformation capabilities to analyze a design and find anti-patterns of CDC design. This visibility has helped us improve our code quality, and is now a part of our continuous integration (CI) workflow.

fplib is a synthesizable SystemVerilog library for working with fixed-point (FP) numbers. This library abstracts out the error-prone task of working with FP numbers, such as keeping track of the integer and fractional bits (the binary point) when doing add/multiply operations. fplib works by (ab)using SystemVerilog interfaces to encapsulate a normal logic vector as well as the parameters for the number of int/frac bits into a single object which can be passed through modules (in the absence of proper language support like in VHDL)

The award-winning SERV is the world's smallest RISC-V CPU and has already proven that you can get a real RISC-V for a fistful of gates. The trade-off is that it is slower than most other RISC-V cores, which is fine for most uses of SERV. But sometimes you need a little more performance and for those cases, we got just the thing for you.

Meet QERV, the quadrupled SERV! QERV is three times faster than SERV while only being approximately 20% larger, which means that it's still the world's smallest RISC-V CPU, only faster. Or why not try HERV, 5 times faster and 50% larger.

This presentation will look deeper into QERV and HERV, what makes them so small and how they compares to SERV when it comes to power efficiency, performance and area. We will also look at future features and optimizations in the pipeline and investigate what you can get for a few gates more.

Europe is stepping up in Open Source Chip Design by funding various parts of the ecosystem. In particular, currently Open Source EDA tools are in the focus, attracting 40+ million Euro in funding.

This presentation gives a brief overview of how FOSSi Foundation played an integral role in this effort and how the community will benefit from, and which challenges are ahead.

Accelerating agile hardware design requires aggressive reuse of libraries and methodologies. While libraries like Basejump STL, PULP Platform Common Cells and Chipyard excel at providing portability layers and low-level components (e.g. FIFOs, memories), and SoCs rely on hardened IP blocks for larger components (e.g. off-chip PHYs, processor cores), there remains a gap in reuseable blocks between these levels.

bsg_pearls bridges this gap by offering a library of mid-level synthesizable components - such as SDR links, DDR links, clock generators, LPDDR controllers - that can be seamlessly integrated into soft designs. Each submodule contains SystemVerilog design files, a synthesizable testbench, vendor-agnostic TCL constraints and technology-agnostic placement guidelines. By construction, pearls are highly runtime configurable and (mostly) decoupled from external timing paths, enabling early hardening in the design process. This drastically reduces full-chip iteration time while maintaining flexibility in immature RTL.

In this talk, I will present the philosophy and architecture of bsg_pearls; explore their use in real-world chip designs; discuss integration plans with open-source tooling; and invite feedback from the open-source hardware community to drive adoption!

In this talk, we will introduce the open silicon education course by using open-source EDA toolchain (Yosys, cocotb, iEDA etc.) on IHP130 open PDK powered by cloud platform, with the primary objective to fill the gap between academic and industry. This course is currently under development and will be released in 2025Q2 with rich materials (lecture notes, slides, hands-on labs) and infrastructure support (RTL2GDS flow, LMS, cloud platform, etc.). Additionally, we will show a full practice on designing an education-oriented test chip (called “retroSoC”) to verify our new end-to-end workflow (Yosys+iEDA+IHP130) with cloud platform. Finally, we will further share more technical details on our EDA cloud platform and explore the performance boundaries by reimplementing some complicated SoCs on cloud platform. We hope this process can help us figure out performance bottleneck and promote the development of open EDA toolchain to make it suitable for various industry application scenario in the future.

svck is an open-source, minimalist linter designed to svck is an open-source, minimalist linter designed to enforce style and consistency rules for SystemVerilog code. It provides a Build Your Own Linter (BYOL) framework, allowing users to define custom linting rules while leveraging built-in checks for naming conventions, encapsulation, line spacing, and more. svck integrates seamlessly into CI/CD pipelines, ensuring maintainable and high-quality HDL code.

Unlike ad-hoc regex or Perl-based scripts, svck is a professional-grade linter built on Google’s open-source Verible parser. This foundation makes it far more scalable, robust, and accurate, ensuring reliable rule enforcement across large and complex codebases. Its modular architecture allows easy customization, enabling users to define new lint rules tailored to their verification and design needs.

This talk will explore svck’s architecture, its use of Verible for syntax parsing, and the flexibility offered by BYOL. We will demonstrate its application in real-world verification workflows and discuss community contributions that continue to shape its development.enforce style and consistency rules for SystemVerilog code.

Creating adequate test content to verify hardware designs across the IP to SoC process presents a a continual challenge for verification engineers. It certainly doesn't help that the unique goals, current verification languages, and restrictions of each verification platform make reuse of test content challenging and effort intensive.

Accellera Portable Stimulus Specification (PSS) language is a test-content modeling language that enables test content reuse from block IP to SoC and across simulation, hardware emulation, and silicon platforms. PSS provides zero-cost abstraction language features that model common verification scenarios, such as concurrency and resource contention, enabling compilation tools to create efficient platform-appropriate implementations.

This talk will provide an example-driven introduction to the PSS language, and provide resources and details of available open source tools that support learning about and using PSS.