Latch-Up 2024

Friday to Sunday April 19–21, 2024 in Boston, MA, USA

The Latch-Up conference is a weekend of presentations and networking dedicated to free and open source silicon. It's an event for the open source digital design community, much like its European sister conference ORConf, run by the FOSSi Foundation.

You are all invited!

The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday April 19 to Sunday April 21 in Boston, MA, USA.

Latch-Up is a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf.

So save the date, register to attend, and submit a presentation or proposal if you have a project or idea on the topic to share!

Questions? Ping the organizers via @LatchUpConf or send an email to latch-up@fossi-foundation.org.

Submit a talk

We encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available.

So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.

Presentations are submitted through the registration process and we will let you know if your presentation was accepted.

Tickets and registration

Attendance of Latch-Up is free of charge. To help us organizing the event, you are required to register on Eventbrite. Please register as soon as possible, as we have to close registrations as soon as the room capacity is reached.

Attendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat.

We ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event.

Sponsoring and volunteering at Latch-Up

Latch-Up is free to attend, but we aim to provide catering and the like during the event. Latch-Up is also a great way to get your company or brand in front of lots of engineers and hackers on the day, and thousands more through recordings of the event. So please get in touch if you'd like to explore sponsorship opportunities.

Latch-Up is organized by volunteers on behalf of the FOSSi Foundation. We are currently looking for more people to help out with arrangements and putting on the event, so please do email us if you would like to volunteer for during the event with setup, AV, or even just local knowledge so we can plan the weekend better.

Venue

Massachusetts Institute of Technology, Cambridge and Wentworth Institute of Technology, Boston

More detailed information coming later.

Programme

Preliminary programme. More to come later.

Beyond EDA lies Edalize

Olof Kindgren

Originally a part of the award-winning FuseSoC, Edalize is now a stand-alone Python library for interfacing with EDA (Electronic Design Automation) tools. It allows users to programmatically construct, manage, and run simulations, synthesis, and other EDA workflows for digital design projects. Edalize abstracts the backend tools by providing a common interface for 40+ different EDA tools such as Verilator, Icarus Verilog, Yosys, Vivado, Quartus, OpenROAD and others.

The purpose of Edalize is to make it easier to integrate EDA tools into other systems and frameworks, such as continuous integration setups, by providing a consistent API. It also aims to simplify the process of running EDA tools across different environments and platforms.

This presentation will look at the latest and upcoming changes to Edalize that intends to make it easier to integrate in existing build setups and more flexible to support more complex workflows.

MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL

Tobias Strauch

Theorem-Proving is also called “Deductive Formal Verification, DFV”. In this presentation I will give an overview of open source DFV projects as well as introduce my own project. I developed the language PDVL to revolutionize design verification. One of the verification disciplines that PDVL will have a major impact on is DFV. In this presentation, I will show how the aspect-oriented and transaction-level based approach of the Programming Design and Verification Language (PDVL) provides important advantages for transforming your design and verification goals into Gallina code that can be used for assertions and theorem proving by "The Rocq Prover” (formerly known as the Coq Proof Assistant). A regular paper on this work was accepted at the DATE 2024 conference. The open-source files can be found here: PDVL specification: https://github.com/cloudxcc/PDVL PDVL examples: https://github.com/cloudxcc/PDVL_Examples MRPHS compiler: https://github.com/cloudxcc/MRPHS

Spade: An HDL Inspired By Modern Software Languages

Frans Skarman

In the software world, the state of the art of programming languages has evolved continuously over the past three decades. In the hardware description domain however, the development has been much slower with most people still using VHDL or Verilog which originated in the 80s. Spade is a new HDL with the goal of bringing innovations and ideas from software languages into the hardware world. In this talk, I will first briefly introduce the basics of the Spade language. Then I will demonstrate how some stand-out features such as native constructs for pipelining, the rich rust-inspired type system, and ports modelled using affine types can be used to increase developer productivity, especially when refactoring or integrating existing code. Spade is an Open Source project licensed under the EUPL-1.2. You can learn more at https://spade-lang.org/

CACE Study: Open source analog and mixed-signal design flow

Tim Edwards

With the recent introduction of multiple open-source foundry process design kits (PDKs), open source digital flows for custom chip design have largely standardized around yosys and OpenROAD/openlane. Open source design flows for analog and mixed-signal circuits have lagged behind. Most designers use a combination of xschem, ngspice, klayout, and magic. But there is little standardization of project structure, specification, testbench methodology, and datasheet generation. The CACE system, originally designed for the Efabless platform, addresses the need for a system around the specification of circuit performance, with a standard way to simulate circuits over all process, voltage, and temperature corners, and automatically collate results into a datasheet of electrical and physical parameters with maximum/typical/minimum values, pass/fail results, and tables and graphs on demand. This presentation explores the capabilities of CACE and looks at current and future development directions.

Switchboard: Calling All Hardware Models

Steven Herbst

Switchboard is a high-performance and easy-to-use tool for simulating a mixture of digital hardware models, developed by Zero ASIC. Models can be represented with RTL simulation, RTL implemented on FPGAs, C++, or Python, with inter-model communication happening over fixed, unidirectional connections that mimic how a real system would be wired together. Under the hood, Switchboard connections are implemented as shared-memory queues, making them quite fast: up to 1 GB/s bandwidth / 200 ns latency. Because the queues have a simple, standardized memory layout, they are convenient to access from RTL implemented on FPGAs. Switchboard powers the multi-chiplet cloud FPGA emulation system on Zero ASIC's website, where it is fast enough to boot Linux and run ML models on emulated hardware in near realtime. We also use Switchboard on a smaller scale for running Python-based block-level tests; its Universal Memory Interface API, combined with its low setup overhead, makes Switchboard an efficient way to write one-off tests. In other words, Switchboard is fast enough to run big workloads, but easy enough to use that it has become a go-to for daily hardware design tasks.

From an Open-Source ISA to Open-Source HW to Open-Source Silicon

Luca Bertaccini

In this talk, we will provide a comprehensive overview of the PULP platform's open-source activities and roadmap: starting from an open-source instruction set architecture (ISA) to open-source hardware IPs to the employment of open-source EDA tools. In addition, we will cover the benefits we experienced thanks to this open-source model, the challenges we overcame in the past years, and the ones we are currently facing.

A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation

Steve Hoover

Every summer since 2005, Google has sponsored students to learn about and contribute to open-source projects in Google Summer of Code (GSoC). Since 2016, the Free and Open Source Silicon (FOSSi) Foundation has served as an "umbrella organization" in Google Summer of Code, coordinating projects related to open-source circuit design and EDA. Transaction-Level Verilog (TL-Verilog) is a technology that has evolved over this period of time, and it has been utilized in numerous projects under FOSSi Foundation since 2018 as well as two this past year in CHIPS Alliance. Student contributions in GSoC have been instrumental in advancing the ecosystem for TL-Verilog, the accessibility of hardware design, and the quality of semiconductor education. This talk will provide a very brief overview of TL-Verilog and survey the contributions of the fifteen GSoC projects that utilized it. These include: FPGA-accelerated web applications, block-based circuit design (like scratch.mit.edu), a virtual FPGA lab, formal verification innovation, a transaction-level component library, a tensor core study, simulation visualization, many-core projects, and TL-Verilog support in other open-source infrastructure and Open MPW shuttles. These projects resulted in publications, conference awards, and prominent blog posts.

HDLAgent, Enhancing Hardware Language in the age of LLMs

Jose Renau

Large Language Models (LLMs) are revolutionizing the programming language landscape, enabling beginners and transforming code generation. This work explores the challenges and implications of integrating LLMs with Hardware Description Languages (HDLs).

Caster: An Open-source E-Ink Controller

Wenting Zhang

In this talk I will present the Caster project. Caster is an open-source low-latency electrophoretics display (like E-Ink) controller soft IP design, offering support for wide range of screens, flexible screen update control, and multiple dithering options. An reference implementation of an Eink monitor using the Caster on an FPGA is also provided, with fully open-source RTL, PCB and enclosure design.

Multiarch in situ; running multiple architectures simultaneously.

Kurt Keville

Modern server architectures now allow us to consider heterogeneous architecture mixes to accommodate particular processing priorities. For instance, it is quite common to have an arm SOC with equal numbers of big and LITTLE cores such as those used in their DynamIQ enabled products. System managers can then decide how to use process migration to maximize allocation of power and speed in the same system. Our work extends this analysis to other products from different vendors and designs.