This talk outlines the University of Toronto ASIC Team's initiative to democratize silicon engineering by leveraging the Free and Open Source Silicon (FOSSi) ecosystem.

By adopting open-source tools the team enables undergraduates to experience the complete design cycle, resulting in tangible tapeouts through services like TinyTapeout. The presentation will detail the team's extracurricular impact—including the university's first IC Design Hackathon—and its strategic partnership with the ECE faculty to rewrite and modernize core course laboratories. This integration of open-source methodologies into both student competitions and formal lab curricula demonstrates a scalable model for making engineering education more practical and industry-relevant.

Mr. Scrub is an open-source, internal scrubber for AMD’s UltraScale FPGAs. We document the algorithms used for SECDED of the device’s configuration frames. We also describe validation of the scrubber using fault injection.

FSMs drive the control plane of hardware: sequences, protocols, arbitration, and recovery logic. Despite language evolution, the way FSMs are written often has not changed. Many "high level" HDLs still express sequencing using the same legacy structure: explicit state variables, explicit transitions, and growing scaffolding as designs evolve. This talk shows a few concrete examples where modern syntax and tooling still lead back to the classic FSM pattern, and why that pattern becomes brittle at scale. Then we focus on the hidden gem: Bluespec. With guarded atomic actions and sequencing as first-class concepts, Bluespec changes the shape of FSM code, making control intent clearer and large stateful behavior more maintainable.

The design of advanced Analog chips‚ especially in photonics, quantum, MEMS, and RF, faces critical challenges due to rigid, outdated EDA tools. Many teams resort to custom Python, C, or MATLAB solutions, which offer flexibility but lack scalability. To bridge this gap, we created GDSFactory, an open-source, python-based Analog Electronic Design Automation software that has been downloaded over 2 million times and adopted by companies, universities, and research organizations worldwide.

Open-source RISC-V cores such as VexRiscv offer flexible architectures for embedded FPGA and ASIC implementations, but instruction cache configurations significantly influence performance, area, and power trade-offs. This work presents a quantitative analysis of instruction cache optimization within the VexRiscv core, evaluating performance impacts across multiple cache configurations in resource-constrained environments. Through synthesis and benchmarking on FPGA and ASIC-targeted workflows, we analyze utilization, and efficiency metrics to identify optimal design trade-offs. Results demonstrate measurable improvements in performance-per-resource metrics. These findings provide practical guidance for designers leveraging VexRiscv in customized RISC-V implementations.

As python-based build systems such as FuseSoC and SiliconCompiler gain adoption across the industry, projects are becoming increasingly tied one ecosystem or another. This lock-in limits teams' ability to use hardware IP and leverage tool flows developed in other ecosystems.

This presentation introduces a new approach for interoperability between build systems, along with a supporting library that enables compatibility between FuseSoC's cores and SiliconCompiler's libraries. By lowering switching costs, we aim to increase IP reuse, reduce engineering duplication, and allow teams to choose the right tool for each stage of the design process

After the shutdown of Efabless in February 2025, Cadence ran their first shuttle on Sky130 with a generous invitation to the open source silicon community. I submitted five chips: Tiny Tapeout TT-06, to compare to the Efabless shuttle run; TT-09, a copy of the original lost Efabless TT-09, and TT-Cad25A, a combination of projects from TT-08 and the never-manufactured TT-10; Chipalooza projects 2, the second of the two planned analog projects chips from the Efabless Chipalooza contest; and Panamax FPGA, a demonstration of the 130-pin "Panamax" frame with a Fabulous FPGA project core. I will present on challenges of the tapeout as well as test results from the manufactured parts.

Open-source silicon reaching real products is the moment the ecosystem matures from a research tool into infrastructure — the same transition Linux made when it started running production servers. Products impose the constraints that drive quality: a battery life target forces low- power verification, a temperature spec forces worst-case timing closure, a BOM cost goal forces die area discipline. These are the rigors that transform open IP blocks from tapeout artifacts into components the industry can trust, and that open custom silicon to the thousands of product companies that have never had access to it. The open-source stack is ready for this — open PDKs, automated RTL-to-GDSII, a proven SoC harness, and shared-wafer shuttles that make silicon accessible. The tools are no longer the barrier. The next step is ours to take.​​​​​​​​​​​​​​​​

Open-source electronic design automation (EDA) tools and accessible fabrication platforms are transforming how integrated circuits are designed, enabling broader participation in silicon development beyond traditional industrial environments. The Chipathon is a global open-source IC design challenge organized under the IEEE Solid-State Circuits Society (SSCS) PICO (Platform for IC Design Outreach) initiative. The program aims to democratize chip design by providing students, educators, and researchers with a structured pathway to design, verify, and potentially fabricate integrated circuits using open-source tools and publicly accessible process design kits.

The Chipathon combines a multi-month design competition with a culminating workshop where participants present their designs, methodologies, and lessons learned. Teams develop innovative circuit blocks and systems across multiple tracks, including digital systems, analog and mixed-signal circuits, AI-assisted design flows, and reusable open-source building blocks. Emphasis is placed on reproducibility, open collaboration, and transparent evaluation through shared design artifacts, verification methodologies, and benchmark metrics.

By integrating education, open-source infrastructure, and real silicon opportunities, Chipathon lowers barriers to entry for integrated circuit design and fosters a new generation of hardware innovators. The program also serves as a testbed for emerging design methodologies—including AI-assisted EDA workflows—and promotes the development of reusable circuit intellectual property for the open-source hardware ecosystem. Through its global participation and collaborative spirit, Chipathon advances the SSCS mission of expanding access to chip design education and accelerating innovation in the semiconductor community.