Welcome to Down Underflow! All you need to know to have a successful conference.

An introduction to and round up of the latest and greatest from the Cocotb project: chip development and verification turbocharger in Python.

An update on wafer.space.

This talk shares lessons from one of the early structured uses of the OpenROAD RTL-to-GDS flow in an Australian ASIC training course delivered through the Semiconductor Sector Service Bureau (S3B). The course used a fully open-source flow built around Yosys for synthesis, OpenSTA for timing analysis, OpenDP for placement, TritonCTS for clock tree synthesis, and TritonRoute for routing. The presentation focuses on practical flow behaviour, setup and integration challenges, and recurring issues observed in real student designs. It concludes with concrete suggestions on how the community can make OpenROAD easier to use, more reliable, and better suited for teaching and large-scale training.

An exploration of open source tooling IP and flows which greatly reduce the barrier to entry for semiconductor startups informed by Morse Micro's experience circa 2016 to today.

SystemVerilog is a challenging language to parse. Thanks to Mike Popoloski's Slang SV frontend, state-of-the-art FOSS parsing of complex SystemVerilog has been achievable. Using Slang, I present two tools: Slingshot and Slander. Slingshot is a SystemVerilog Language Server Protocol (LSP) with a focus on accurate and fast completion, whereas Slander is a tool for minimising and mutating SV for the purposes of fuzzing.

All HDL simulators follow the same process (analyse, elaborate and simulate) though each uses its own variation of these commands. Similarly, all HDL synthesis tools follow the same flow (synthesise, place and route, and generate bitstream). hdlworkflow abstracts away these tool-specific commands, making project setup and usage fast and effortless.

In 2025 I launched COMP6420 Hardware Security at UNSW. This new course explores the principles and practices of hardware security, covering topics such as side-channel attacks, hardware trojans, cryptographic implementations in hardware, and more. Everything is designed around practical hands-on experiences and labs, ensuring that students not only learn the theoretical aspects of hardware security but also how to apply these concepts in real-world scenarios. In this talk, I will discuss how I achieved this through the use of the open-source OSS-CAD-Suite as well as the development of a bespoke educational hardware platform, the Hackster, which I also release under CC BY-SA.

This presentation will cover Zamlet, a RISC-V vector processing unit that scales to large numbers of lanes using a mesh network for interlane communication rather than a crossbar. I'll present some modelling work and some initial area estimates.

Despite the growing importance of custom blocks and cells in modern chips, custom-circuit design still relies heavily on manual optimization. In this talk, we argue that a language-driven representation and toolchain for transistor-level netlists can serve as infrastructure to enable transistor-level design automation for optimizations that scale to larger designs. This talk will present one step in this direction: We introduce TransiLog, a DSL for CMOS transistor networks. TransiLog combines behavioral and topological semantics to represent transistor-level structures. Using state-of-the-art rewriting techniques, we show how to optimize transistor netlists for multiple PPA goals using the same representation. TransiLog also emits SPICE netlists compatible with existing transistor-level physical design backends and offers a foundation for future hybrid flows that combine custom-circuit and cell-level optimization.

The group will present their work on the Serengeti SoC and LionOS

ASIC prototyping flows struggle with complicated toolchain management, ad-hoc debug infrastructure and tight coupling to vendor IP. This talk will describe a flexible approach to engineering emulation clusters, scaling from budget FPGAs to large emulation platforms.