The FOSSi Foundation is happy to announce that we have been granted eight slots by Google to support projects and students for another year's edition of Google Summer of Code. We are thankful for all mentors who volunteered to supervise students, and we're looking forward to a great summer working together on Free and Open Source Silicon projects.
These projects's are our "GSoC Class of 2020". The students will introduce themselves over the coming days to the various projects, please give them a warm welcome!
Mentored by Kunal Gulati and Jonathan Balkind.
This project involves a heterogeneous-ISA system based on a BYOC (Bring Your Own Core) framework. This provides a cache coherent, manycore research framework meant to support a variety of ISAs. The ao486 core having a x86 ISA, provides support for legacy code and is one of the few open source CISC ISAs. The initial approach to integration involved connecting BYOC through the Avalon interface. In this project, work is done with the bare interface of ao486 to interface it with BYOC to maintain cache coherency across all cores.
Adding Deployment-Phase Tracing Features (using Timeprints) To Open SoC Debug Platform (Rehab Massoud)
Mentored by Philipp Wagner and Stefan Wallentowitz
This project aims at adding deployment-phase tracing features, to the Open SoC Debug platform existing tracing features. OSD is still following the traditional tracing methodologies, which are mainly concerned with instructions executed, cache miss/hit rates monitoring, registers monitoring...etc. While these methods are useful for debugging and tracing at development time, they produce huge amounts of data which makes them very un-efficient to use during deployment. Recently, a new methodology for deployment-time efficient tracing, based on Timeprints, was proposed. Timeprints are periodic summaries of the temporal behavior of the traced signals. They are lightweight logs, triggered by executions, and can only produce useful information with off-line ""Reconstruction"". In this Project, I want to make deployment-time tracing and checking, enabled by Timeprints, part of the OSD platform. This includes work on two fronts: 1) Developing deployment-phase trace specifications within the OSD specifications, and 2) Developing standard modules to support this in OSD. In the third phase, a working implementation with the newly released RISC-V trace specifications is expected.
Mentored by Ákos Hadnagy, Jonathan Balkind and Steve Hoover
WARP-V is an open-source and highly flexible and configurable CPU core with customisable ISA and pipelines written in the emerging “Transaction-Level” modelling. OpenPiton is an open-source, general-purpose, multi-threaded manycore framework for heterogeneous architecture research. This project aims to evolve WARP-V further by adding necessary support for memory, microarchitecture extensions etc., and make it RISC-V Linux compatible and then integrate it with the OpenPiton-derived Bring Your Own Core (BYOC) Framework. This would open the doors for the first Linux-capable processor based on TL-Verilog and easy scaling to multicore heterogeneous implementation with OpenPiton.
Mentored by Aliaksei Chapyzhenka and Olof Kindgren
Digital logic designs can become very complex. Like many fields of engineering, visual analysis and debugging tools can greatly aid developers, reverse-engineers, and teachers. Existing methods to render digital logic designs have numerous flaws unfortunately. My project aims to create an entirely new netlist visualization tool. This new tool will feature multiple ways of displaying circuit designs without overwhelming the user. It will also feature close integration with other tools in the logic designer’s arsenal, giving the user visual design information directly beside signal traces and source code.
Mentored by Ang Li (primary), Jonathan Balkind and Stefan Wallentowitz
The goal of the project is to automate and augment the verification of the custom FPGA and the bitstream with Cocotb, an open-source framework for verifying VHDL/ Verilog RTL using python. At the end of the project, users will get to generate a bitstream file and also know whether it is correct or not automatically.
Mentored by Florian Zaruba, Nils Wistoff and Jonathan Balkind
RISC-V is an open source ISA, and supports 32-bit, 64-bit, and 128-bit implementations. It is designed to be extendable in future to cater for different application needs. Both privileged and non-privileged instructions are included in RISC-V ISA. Recently, hypervisor extensions were released. These extensions are expected not to change much, and to be ratified in near future. The proposed extensions have two new modes titled hypervisor-extended supervisor mode (HS), virtual S-mode (VS-mode), and virtual U-mode (VU-mode).. Secondly, Ariane is a 6-stage, single issue, in-order CPU, and is an implementation of 64-bit RISC-V ISA being developed at ETH Zurich. This project aims to add proposed extensions to Ariane core.
Mentored by Steve Hoover and Ákos Hadnagy
The WARP-V RISC-V core generator was developed in 2018, it is the most-configurable, most-adaptable open-source RISC-V CPU core generator, taking advantage of advanced digital design features of TL-Verilog. Till now WARP-V has support for RV32I base instruction set architecture and is formally verified using Risc-V formal. My proposal is to implement RV32F(Single Precision Floating-point) Unit extensions to the Warp-V core by using a "hard float by Berkeley" library written in chisel, which also supports IEEE 754 single-precision floating-point unit. My proposal is also to introduce Virtual Memory support(TLB) in Warp-V and to complete the implementation of Bit-Manipulation Instructions.
Mentored by Jonathan Balkind and Jeff Bush
In this project, we propose to integrate the Nyuzi core with the OpenPiton platform. To be able to model and conduct research on heterogeneous systems, it is important that the community has access to platforms that allow them to run applications that are not restricted by the computational-limitations of the CPU-cores, but also allows them to run more recent workloads such as those belonging to the domain of machine learning and deep learning. We believe that the integration of the OpenPiton core with Nyuzi would provide a first of its kind, completely synthesizable, open-source, multi-core, heterogeneous platform, that would provide simulation, emulation, and implementation capabilities to the researchers.